Executing flash storage access requests
A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.
1. A method for accessing a processor-bus-connected flash storage module (PFSM) operatively coupled to a processor via a processor bus, the PFSM comprising a flash memory, a buffer memory, and command registers, mapped into an address space of the processor, the method comprising:
receiving one or more parameters of a page access request from the processor via the processor bus using the command registers;
allocating a context for the page access request in the buffer memory;
storing the one or more parameters of the page access request in the context;
adding, in response to the one or more parameters comprising a trigger parameter, the context to a pre-determined schedule;
reading the context according to the pre-determined schedule; and
issuing a command of the processor bus in conjunction with performing a flash memory access to transfer data between the PFSM and the processor as specified in the context.
2. The method of claim 1 , further comprising:
scheduling a direct memory access (DMA) operation responsive to receiving the trigger parameter,
wherein the DMA operation comprises performing the flash memory access and the command of the processor bus.
3. The method of claim 1 , further comprising:
generating an interrupt to the processor when the command of the processor bus and the flash memory access are completed.
4. The method of claim 1 , wherein the flash memory and a cache partition of the buffer memory forms a memory hierarchy of the PFSM, the method further comprising:
performing a cache operation according to a cache policy of the memory hierarchy responsive to receiving the trigger parameter, wherein the flash memory access is scheduled responsive to performing the cache operation.
5. The method of claim 4 , wherein the PFSM further comprises a flash page address mapping table, the method further comprising:
generating, based on the flash page address mapping table, a cached flash page address in the cache partition from a flash page address comprised in the one or more parameters,
wherein the cache operation is based on the cached flash page address.
6. The method of claim 4 , wherein the PFSM further comprises a virtual address mapping table for implementing a virtual memory paging device, the method further comprising:
generating, based on the virtual address mapping table, at least one of a flash page address in the flash memory and a cached flash page address in the cache partition from a virtual address comprised in the one or more parameters,
wherein the cache operation and the flash memory access are based on the at least one of the flash page address in the flash memory and the cached flash page address in the cache partition.