A display device includes: plural pixel groups each including pixel circuits; plural scanning lines that are each connected to the pixel circuits included in any one of the pixel groups; a clock signal supply circuit that supplies a clock signal including a pulse signal; a shift register circuit that selectively transmits the pulse signal to the scanning lines in a predetermined order; and data signal lines that are connected to the pixel circuits and that supply a data signal to the pixel circuits included in the pixel group to be scanned. The period of the pulse signal supplied to some of the scanning lines is longer than the period of the pulse signal supplied to the other scanning lines, or the data signal is transmitted by the transistors included in the pixel circuits.
1. A display device comprising:
a plurality of pixel groups each including pixel circuits;
a plurality of scanning lines that are each disposed to correspond to any one of the plurality of pixel groups and that are connected to the pixel circuits included in the corresponding pixel group;
a clock signal supply circuit that supplies a clock signal including a pulse signal as a potential scanning the corresponding pixel group in a period in which each of the plurality of pixel groups is scanned;
a shift register circuit that selectively transmits the pulse signal to the plurality of scanning lines in a predetermined order; and
data signal lines that are connected to the pixel circuits included in the plurality of pixel groups and that supply a data signal to the pixel circuits included in the pixel group to be scanned;
wherein the clock signal supply circuit supplies the clock signal so that a period of the pulse signal supplied to some of the plurality of scanning lines is longer than a period of the pulse signal supplied to the other scanning lines;
wherein the shift register circuit includes a plurality of elementary circuits that transmit the pulse signal from the clock signal supply circuit to any of the plurality of scanning lines;
wherein each elementary circuit includes:
a first transistor that is disposed between the clock signal line and the corresponding scanning line; and
a second transistor that is diode-connected and that supplies the pulse signal to be output to the scanning line in a predetermined number before the corresponding scanning line to a gate electrode of the first transistor; and
wherein a width of a source electrode and a drain electrode of the second transistor included in an elementary circuit in which the period in which the supplied pulse signal serves as a scanning potential is long is smaller than a width of a source electrode and a drain electrode of the second transistor included in an other elementary circuit.
2. The display device according to claim 1 , wherein the clock signal supply circuit supplies the clock signal so that the period of the pulse signal supplied to the pixel group to be scanned in a case that the polarity of the data signal supplied to the pixel circuits included in the pixel group to be scanned is different from the polarity of the data signal supplied to the pixel circuits included in the pixel group which is scanned just before the pixel group to be scanned is longer than a case in which the polarities of the two data signals are not different from each other.
3. The display device according to claim 2 , further comprising:
a plurality of clock signal lines that supply the clock signal from the clock signal supply circuit to the shift register circuit,
wherein the clock signal supply circuit repeatedly supplies the pulse signal to the plurality of clock signal lines sequentially from the first clock signal line, and
wherein the data signal lines supply the data signal changed in polarity every selection of predetermined number of the pixel groups, and the predetermined number of the pixel groups is any one of divisors other than 1 of the number of clock signal lines.
4. The display device according to claim 1 ,
wherein each elementary circuit further includes:
a capacitor that stores a potential difference generated due to the potential of the pulse signal supplied from the second transistor and that turns on the first transistor until the potential difference is reset; and
a third transistor that resets the potential difference stored in the capacitor on the basis of the pulse signal output to the scanning line in a predetermined number after the scanning line to which the elementary circuit transmits the pulse signal.