IP Library Granted Patent US 8,742,556
Granted Patent B2
US 8,742,556 · App. 13/349,993 · Granted Jun 3, 2014

Semiconductor module

Inventors: Takuya Kadoguchi (Toyota, JP); Tomomi Okumura (Toyota, JP); Tatsuya Miyoshi (Nagoya, JP)
Assignee: Toyota Jidosha Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,742,556
App. No.
13/349,993
Granted
Jun 3, 2014
Kind
B2
Abstract

A semiconductor module comprises: a metal block; a semiconductor device installed via a solder layer in a semiconductor device installation area on a surface of the metal block; and a molded portion formed by molding a resin on the metal block and the semiconductor device; wherein the surface of the metal block includes a plating area and a roughened area, and the semiconductor device installation area is provided in the plating area.

Claims (14)

1. A semiconductor module comprising:

a metal block; a semiconductor device installed via a solder layer in a semiconductor device installation area on a surface of the metal block; and

a molded portion formed by molding a resin on the metal block and the semiconductor device;

a plating area includes a plurality of concave portions formed therein; and

a roughened area is provided around the plating area,

wherein the surface of the metal block includes a plating area and a roughened area, and the semiconductor device installation area is provided in the plating area.

2. The semiconductor module of claim 1 , wherein the plating area is formed in a strip form with respect to the metal block.

3. The semiconductor module of claim 2 , wherein the roughened area is formed in a strip form on opposite sides of the plating area.

4. The semiconductor module of claim 1 , wherein the surface of the metal block include an upper surface of a metal plate, the metal plate being formed of a material different from that of the metal block and being press-fitted to a part of the metal block;

the upper surface of the metal plate is made be a roughened area; and

an area of the surface of the metal block except for the upper surface of the metal plate is made be the plating area.

5. The semiconductor module of claim 1 , wherein a plurality of the semiconductor device installation areas are provided on the surface of the metal block.

6. A hybrid system including the semiconductor module of claim 1 .

7. The semiconductor module of claim 1 , wherein the concave portions are not formed in the semiconductor device installation area on the surface of the metal block.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 052281/0019 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2012
From: KADOGUCHI, TAKUYA; OKUMURA, TOMOMI; MIYOSHI, TATSUYA
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 027529/0570 →
Priority Claims (1)
JP 2011-005961 · Jan 14, 2011 · national
Continuity (1)
Related Publication 20120181679A1 · Jul 19, 2012