IP Library Granted Patent US 8,466,822
Granted Patent B2
US 8,466,822 · App. 13/352,615 · Granted Jun 18, 2013

Analog-to-digital conversion apparatus and signal processing system

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Quick Facts
Patent No.
US 8,466,822
App. No.
13/352,615
Granted
Jun 18, 2013
Kind
B2
Abstract

An AD conversion apparatus includes: a first AD converter for converting an input analog signal into a first digital signal; a second AD converter for converting an analog signal obtained as a result of multiplying the input analog signal by a coefficient α into a second digital signal; a first computing unit for multiplying the first digital signal output by the first AD converter by α 2 obtained as a result of squaring the coefficient α; a second computing unit for multiplying the second digital signal output by the second AD converter by α −1 which is the reciprocal of the coefficient α; and a third computing unit for computing a difference between a first computation result output by the first computing unit and a second computation result output by the second computing unit and outputting the difference as a result of AD conversion carried out on the input analog signal.

Claims (29)

1. An analog-to-digital conversion apparatus comprising:

a first analog-to-digital converter configured to convert an input analog signal into a first digital signal;

a second analog-to-digital converter configured to convert an analog signal obtained as a result of multiplying said input analog signal by a coefficient α into a second digital signal;

a first computing unit configured to multiply said first digital signal output by said first analog-to-digital converter by α 2 obtained as a result of squaring said coefficient α;

a second computing unit configured to multiply said second digital signal output by said second analog-to-digital converter by α −1 which is the reciprocal of said coefficient α; and

a third computing unit configured to compute a difference between a first computation result output by said first computing unit and a second computation result output by said second computing unit and to output said difference as a result of analog-to-digital conversion carried out on said input analog signal.

2. The analog-to-digital conversion apparatus according to claim 1 , wherein:

said first and second analog-to-digital converters are each created as a pipeline analog-to-digital converter including an input capacitor for sampling an input signal at the input stage; and

the capacitance of said input capacitor included in said first analog-to-digital converter is made different from the capacitance of said input capacitor included in said second analog-to-digital converter.

3. The analog-to-digital conversion apparatus according to claim 2 , wherein

the capacitance of said input capacitor included in said second analog-to-digital converter is made smaller than the capacitance of said input capacitor included in said first analog-to-digital converter.

4. The analog-to-digital conversion apparatus according to claim 1 , wherein:

said first and second analog-to-digital converters are each created as a delta-sigma analog-to-digital converter;

each of said delta-sigma analog-to-digital converters includes

at least one integrator with an integration capacitor,

a quantizer configured to quantize a signal output by said integrator in order to generate and output a digital signal,

at least one digital-to-analog converter configured to convert said digital signal generated by said quantizer into an analog signal and feed said analog signal back to the input side of said integrator through a load resistor, and

an input resistor configured to receive an input signal; and

the resistances of said load and input resistors included in said first analog-to-digital converter and the capacitance of said integration capacitor included in said first analog-to-digital converter are made different from respectively the resistances of said load and input resistors included in said second analog-to-digital converter and the capacitance of said integration capacitor included in said second analog-to-digital converter.

5. The analog-to-digital conversion apparatus according to claim 4 , wherein

the resistances of said load and input resistors included in said second analog-to-digital converter and the capacitance of said integration capacitor included in said second analog-to-digital converter are made greater than respectively the resistances of said load and input resistors included in said first analog-to-digital converter and the capacitance of said integration capacitor included in said first analog-to-digital converter.

6. A signal processing system comprising

an analog-to-digital conversion apparatus for converting an input analog signal generated by an analog-signal processing system into an output digital signal, wherein

said analog-to-digital conversion apparatus includes:

a first analog-to-digital converter configured to convert an input analog signal into a first digital signal;

a second analog-to-digital converter configured to convert an analog signal obtained as a result of multiplying said input analog signal by a coefficient α into a second digital signal;

a first computing unit configured to multiply said first digital signal output by said first analog-to-digital converter by α 2 obtained as a result of squaring said coefficient α;

a second computing unit configured to multiply said second digital signal output by said second analog-to-digital converter by α −1 which is the reciprocal of said coefficient α; and

a third computing unit configured to compute a difference between a first computation result output by said first computing unit and a second computation result output by said second computing unit and to output said difference as a result of analog-to-digital conversion carried out on said input analog signal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040419/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2012
From: NIWA, ATSUMI; UENO, YOSUKE
To: SONY CORPORATION
Reel/Frame 027824/0987 →