Multiple sign bit hiding within a transform unit
View Patent ↗Methods of encoding and decoding for video data are described for encoding or decoding coefficients for a transform unit. In particular, the sign bits for the non-zero coefficients are encoded using sign bit hiding. Two or more sets of coefficients are defined for the transform unit and a sign bit may be hidden for each set, subject to satisfaction of a threshold test. The sets may correspond to coefficient groups that are otherwise used in multi-level significance map encoding and decoding.
1. A method of decoding a bitstream of encoded video by reconstructing coefficients for a transform unit, the bitstream encoding two or more sets of sign bits for the transform unit, each set of sign bits corresponding to a respective set of coefficients for the transform unit, wherein each sign bit indicates the sign of a corresponding non-zero coefficient within the respective set, the method comprising:
for each of the two or more sets of sign bits,
summing an absolute value of the coefficients for the respective set corresponding to that set of sign bits to obtain a parity value; and
assigning a sign to one of the coefficients within the respective set based on whether the parity value is even or odd.
2. The method claimed in claim 1 , wherein each of the respective sets of coefficients corresponds to a respective 4×4 coefficient block.
3. The method claimed in claim 1 , wherein each of the respective sets of coefficients corresponds to a group of respective 4×4 coefficient blocks, and wherein the coefficient blocks in each of the groups are consecutive blocks in a block-level scan order.
4. The method claimed in claim 1 , wherein the method further comprises determining that the number of coefficients within the respective set of coefficients between a first non-zero coefficient and last non-zero coefficient in a scan order exceeds a threshold value.
5. The method claimed in claim 1 , wherein assigning includes making the one of the coefficients negative if the parity value is odd and leaving the one of the coefficients positive if the parity value is even.
6. A decoder for decoding a bitstream of encoded data to reconstruct coefficients for a transform unit, the bitstream encoding two or more sets of sign bits for the transform unit, each set of sign bits corresponding to a respective set of coefficients for the transform unit, wherein each sign bit indicates the sign of a corresponding non-zero coefficient within the respective set, the decoder comprising:
a processor;
a memory; and
a decoding application stored in memory and containing instructions for configuring the processor to
for each of the two or more sets of sign bits,
sum an absolute value of the coefficients for the respective set corresponding to that set of sign bits to obtain a parity value, and
assign a sign to one of the coefficients within the respective set based on whether the parity value is even or odd.
7. The decoder claimed in claim 6 , wherein each of the respective sets of coefficients corresponds to a respective 4×4 coefficient block.
8. The decoder claimed in claim 6 , wherein each of the respective sets of coefficients corresponds to a group of respective 4×4 coefficient blocks, and wherein the coefficient blocks in each of the groups are consecutive blocks in a block-level scan order.
9. The decoder claimed in claim 6 , wherein the processor is further configured to determine that the number of coefficients within the respective set of coefficients between a first non-zero coefficient and last non-zero coefficient in a scan order exceeds a threshold value.
10. The decoder claimed in claim 6 , wherein the processor is configured to assign a sign by making the one of the coefficients negative if the parity value is odd and leaving the one of the coefficients positive if the parity value is even.
11. A non-transitory processor-readable medium storing processor-executable instructions which, when executed, configures one or more processors to perform the method claimed in claim 1 .
12. A method of encoding a bitstream of video by encoding sign bits for coefficients for a transform unit, the method comprising:
for each of two or more sets of coefficients for the transform unit,
summing an absolute value of the coefficients for that set to obtain a parity value;
determining that a sign of one of the coefficients in that set does not correspond to the parity value; and
adjusting a level of a coefficient in that set by one in order to change the parity value to correspond to the sign of one of the coefficients.
13. The method claimed in claim 12 , further comprising, for each of the two or more sets of coefficients, encoding sign bits for all non-zero coefficients in that set except for the one of the coefficients.
14. The method claimed in claim 12 , wherein the two or more sets of coefficients each comprise a respective 4×4 coefficient block.
15. The method claimed in claim 12 , wherein each of the sets of coefficients corresponds to a group of respective 4×4 coefficient blocks, and wherein the coefficient blocks in each of the groups are consecutive blocks in a block level scan order.
16. The method claimed in claim 12 , wherein the method further comprises determining that the number of coefficients within the set of coefficients between a first non-zero coefficient and last non-zero coefficient in a scan order exceeds a threshold value.
17. The method claimed in claim 12 , wherein adjusting a level includes selecting the coefficient in the set to be adjusted using rate-distortion optimization.
18. The method claimed in claim 17 , wherein the rate-distortion optimization uses a predefined cost metric for evaluating a rate cost.
19. An encoder for encoding a bitstream of video by encoding sign data for coefficients for a transform unit, the encoder comprising:
a processor;
a memory; and
an encoding application stored in memory and containing instructions for configuring the processor to
for each of two or more sets of coefficients for the transform unit,
summing an absolute value of the coefficients for that set to obtain a parity value,
determining that a sign of one of the coefficients in that set does not correspond to the parity value, and
adjusting a level of a coefficient in that set by one in order to change the parity value to correspond to the sign of one of the coefficients.
20. The encoder claimed in claim 19 , wherein the processor is further configured to, for each of the two or more sets of coefficients, encode sign bits for all non-zero coefficients in that set except for the one of the coefficients.
21. The encoder claimed in claim 19 , wherein the two or more sets of coefficients each comprise a respective 4×4 coefficient block.
22. The encoder claimed in claim 19 , wherein each of the sets of coefficients corresponds to a group of respective 4×4 coefficient blocks, and wherein the coefficient blocks in each of the groups are consecutive blocks in a block level scan order.
23. The encoder claimed in claim 19 , wherein the processor is further configured to determine that the number of coefficients within the set of coefficients between a first non-zero coefficient and last non-zero coefficient in a scan order exceeds a threshold value.
24. The encoder claimed in claim 19 , wherein the processor is configured to adjust a level by selecting the coefficient in the set to be adjusted using rate-distortion optimization.
25. The encoder claimed in claim 24 , wherein the rate-distortion optimization uses a predefined cost metric for evaluating a rate cost.
26. A non-transitory processor-readable medium storing processor-executable instructions which, when executed, configures one or more processors to perform the method claimed in claim 12 .