Optical receiver

1. An optical receiver for receiving an optical signal that has been subjected to quadrature phase modulation, comprising:

at least two independent CDR circuits for clock extraction, identification and data regeneration of at least two electric signals regenerated from the received optical signal that has been subjected to the quadrature phase modulation;

a synchronization circuit to synchronize at least two first data strings respectively output from the CDR circuits;

a bit shift circuit to bit shift at least one of at least two second data strings output from the synchronization circuit;

a pattern changing circuit to lane swap and polarity invert at least one of the at least two second data strings output from the bit shift circuit;

a multiplexing circuit to multiplex at least two third data strings output from the pattern changing circuit;

a signal check circuit to verify multiplexed data output from the multiplexing circuit; and

a bit shift pattern change control circuit connected to control the bit shift circuit and the pattern changing circuit based on a result of data verification from the signal check circuit, detect a correct combination of correct regenerated data, and establish signal conduction,

wherein the bit shift pattern change circuit repeatedly changes control contents of the bit shift circuit and the pattern changing circuit until the result of the data verification output from the signal check circuit becomes a predetermined result, and detects the correct combination of the correct regenerated data to establish signal conduction,

wherein, when multiplexed data output from the multiplexing circuit in a case where the bit shift circuit and the pattern changing circuit are controlled with a first control content and multiplexed data output from the multiplexing circuit in a case where the bit shift circuit and the pattern changing circuit are controlled with a second control content are the same, the bit shift pattern change control circuit controls the bit shift circuit and the pattern changing circuit with one of the first control content or the second control content, and

wherein the bit shift pattern change control circuit controls so as to verify one of an odd number of bits or an even number of bits among the multiplexed data.

2. An optical receiver for receiving an optical signal that has been subjected to quadrature phase modulation, comprising:

two independent CDR circuits for clock extraction, identification and data regeneration of two electric signals regenerated from the received optical signal that has been subjected to the quadrature phase modulation;

a synchronization circuit to synchronize two first data strings respectively output from the two independent CDR circuits;

a bit shift circuit to bit shift one of two second data strings output from the synchronization circuit;

a pattern changing circuit to lane swap and polarity invert one of the two second data strings output from the bit shift circuit;

a multiplexing circuit to multiplex two third data strings output from the pattern changing circuit;

a signal check circuit to verify multiplexed data output from the multiplexing circuit; and

a bit shift pattern change control circuit to control the bit shift circuit and the pattern changing circuit based on a result of the data verification output from the signal check circuit, detect a correct combination of correct regenerated data, and establish signal conduction,

wherein the bit shift pattern change control circuit repeatedly changes control contents of the bit shift circuit and the pattern changing circuit until the result of the data verification output from the signal check circuit becomes a predetermined result, and detects the correct combination of the correct reproduction data to establish the signal conduction,

wherein the bit shift pattern change control circuit controls the bit shift circuit to set a bit shift amount used to bit shift the one of the two data strings to one of an even number of bits or an odd number of bits, and

wherein the bit shift pattern change control circuit controls so as to verify an odd number of bits or an even number of bits among the multiplexed data.

3. The optical receiver according to claim 1 , wherein the bit shift pattern change control circuit controls so as to verify data which consist of the bit shift of the multiplexed data, the polarity inversion of the multiplexed data, and the bit shift and the polarity inversion of the multiplexed data.

4. An optical receiver for receiving an optical signal that has been subjected to quadrature phase modulation, comprising:

at least two independent CDR circuits for extracting clock and identifying and regenerating data from a regenerated electric signal;

a synchronization circuit for synchronizing outputs of the at least two independent CDR circuits;

a circuit including a bit shift circuit having a bit shifting function and a pattern changing circuit having a lane swapping function and a polarity inversion function;

a multiplexing circuit for multiplexing at least two of first data strings;

a signal check circuit for performing data verification of multiplexed data output from the multiplexing circuit; and

a bit shift pattern change control circuit having functions of controlling the bit shift circuit and the pattern changing circuit based on a result of the data verification output from the signal check circuit, detecting a correct combination of correct regenerated data, and establishing signal conduction,

wherein at least two electric signals regenerated from the optical signal that has been subjected to the quadrature phase modulation are input to the at least two independent CDR circuits, respectively,

wherein at least two second data strings output from the at least two independent CDR circuits, respectively, are input to the synchronization circuit,

wherein at least two third data strings output from the synchronization circuit are input to the circuit,

wherein the multiplexing circuit multiplexes the at least two first data strings output via the circuit,

wherein the bit shift pattern change control circuit repeatedly changes control contents of the bit shift circuit and the pattern changing circuit until the result of the data verification output from the signal check circuit becomes a predetermined result, and detects the correct combination of the correct regenerated data to establish the signal conduction, and

wherein, when multiplexed data output from the multiplexing circuit in a case where the bit shift circuit and the pattern changing circuit are controlled with a first control content and multiplexed data output from the multiplexing circuit in a case where the bit shift circuit and the pattern changing circuit are controlled with a second control content are the same, the bit shift pattern change control circuit controls the bit shift circuit and the pattern changing circuit with one of the first control content or the second control content.