Semiconductor device and structure
View Patent ↗A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact is aligned to the first transistors with less than about 40 nm alignment error, a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.
1. A semiconductor device, comprising:
a first layer comprising monocrystalline material and first transistors, said first transistors overlaid by a first isolation layer;
a second layer comprising second transistors and overlaying said first isolation layer, said second transistors comprising a monocrystalline material;
at least one contact to said second transistors,
wherein said at least one contact is aligned to said first transistors with less than about 40 nm alignment error,
a first set of external connections underlying said first layer to connect said device to external devices;
a second set of external connections overlying said second layer to connect said device to external devices; and
an interconnection layer in-between said first layer and said second layer,
wherein said interconnection layer comprises copper or aluminum.
2. The semiconductor device according to claim 1 ,
wherein said second transistors comprise P type transistors and N type transistors.
3. The semiconductor device according to claim 1 , further comprising:
a back-bias structure for at least one of said second transistors.
4. The semiconductor device according to claim 1 ,
wherein said second layer comprises a node for wireless connection to external devices.
5. The semiconductor device according to claim 1 ,
wherein said first set of external connections comprise through-silicon-vias (“TSV”).
6. The semiconductor device according to claim 1 ,
wherein said second set of external connections comprise micro-bumps.
7. The semiconductor device according to claim 1 ,
wherein said second transistors are horizontally oriented transistors.
8. A semiconductor device, comprising:
a first layer comprising monocrystalline material and first transistors, said first transistors overlaid by a first isolation layer;
a second layer comprising second transistors and overlaying said first isolation layer, said second transistors comprising a monocrystalline material;
at least one contact to said second transistors,
wherein said at least one contact is aligned to said first transistors with less than about 40 nm alignment error,
a first set of external connections underlying said first layer to connect said device to external devices; and
a second set of external connections overlying said second layer to connect said device to external devices,
wherein said second layer comprises a node for wireless connection to external devices.
9. The semiconductor device according to claim 8 ,
wherein said second transistors comprise P type transistors and N type transistors.
10. The semiconductor device according to claim 8 , further comprising:
a back-bias structure for at least one of said second transistors.
11. The semiconductor device according to claim 8 , further comprising:
an interconnection layer in-between said first layer and said second layer,
wherein said interconnection layer comprises copper or aluminum.
12. The semiconductor device according to claim 8 ,
wherein said first set of external connections comprise through-silicon-vias (“TSV”).
13. The semiconductor device according to claim 8 ,
wherein said second set of external connections comprise micro-bumps.
14. The semiconductor device according to claim 8 ,
wherein said second transistors are horizontally oriented transistors.
15. A semiconductor device, comprising:
a first layer comprising monocrystalline material and first transistors, said first transistors overlaid by a first isolation layer;
a second layer comprising second transistors and overlaying said first isolation layer, said second transistors comprising a monocrystalline material;
at least one contact to said second transistors,
wherein said at least one contact is aligned to said first transistors with less than about 40 nm alignment error,
a first set of external connections underlying said first layer to connect said device to external devices; and
a second set of external connections overlying said second layer to connect said device to external devices.
16. The semiconductor device according to claim 15 ,
wherein said second transistors comprise P type transistors and N type transistors.
17. The semiconductor device according to claim 15 , further comprising:
a back-bias structure for at least one of said second transistors.
18. The semiconductor device according to claim 15 , further comprising:
an interconnection layer in-between said first layer and said second layer,
wherein said interconnection layer comprises copper or aluminum.
19. The semiconductor device according to claim 15 , wherein said first set of external connections comprise through-silicon-vias (“TSV”).
20. The semiconductor device according to claim 15 ,
wherein said second transistors are horizontally oriented transistors.