IP Library Granted Patent US 8,547,175
Granted Patent B2
US 8,547,175 · App. 13/355,736 · Granted Oct 1, 2013

Output circuit

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Quick Facts
Patent No.
US 8,547,175
App. No.
13/355,736
Granted
Oct 1, 2013
Kind
B2
Abstract

Provided is an output circuit capable of allowing a more sufficient output current to flow. When a drain current of a PMOS transistor ( 12 ) is large, a PMOS transistor ( 13 ) operates in the non-saturation region. At this time, gate voltages of NMOS transistors ( 14 and 17 ) have risen to around a power supply terminal voltage. Therefore, a gate-source voltage of an NMOS transistor ( 17 ) increases, and a sufficient output current flows.

Claims (22)

1. An output circuit for amplifying a signal input to an input terminal and outputting the amplified signal from an output terminal, comprising:

a first MOS transistor of a first conductivity type including a gate connected to the input terminal, a source connected to a first power supply terminal, and a drain connected to the output terminal;

a second MOS transistor of the first conductivity type including a gate connected to the input terminal and a source connected to the first power supply terminal;

a first current source including one terminal connected to a drain of the second MOS transistor of the first conductivity type and another terminal connected to a second power supply terminal;

a current mirror circuit comprising a third MOS transistor of the first conductivity type and a fourth MOS transistor of the first conductivity type, for mirroring a current corresponding to a difference between a current of the first current source and a drain current of the second MOS transistor of the first conductivity type, the third MOS transistor of the first conductivity type including a gate and a drain which are connected to the one terminal of the first current source, the fourth MOS transistor of the first conductivity type including a gate connected to a gate of the third MOS transistor of the first conductivity type;

a first MOS transistor of a second conductivity type including a gate and a drain which are connected to a drain of the fourth MOS transistor of the first conductivity type;

a second current source including one terminal connected to a source of the first MOS transistor of the second conductivity type and another terminal connected to the second power supply terminal;

a third current source including one terminal connected to the first power supply terminal;

a second MOS transistor of the second conductivity type including a gate connected to another terminal of the third current source, a source connected to the one terminal of the second current source, and a drain connected to the first power supply terminal;

a third MOS transistor of the second conductivity type including a gate and a drain which are connected to the another terminal of the third current source and a source connected to the second power supply terminal; and

a fourth MOS transistor of the second conductivity type including a gate connected to the drain of the first MOS transistor of the second conductivity type, a source connected to the second power supply terminal, and a drain connected to the output terminal.

2. An output circuit according to claim 1 , further comprising:

a first cascode circuit provided to the one terminal of the first current source; and

a second cascode circuit provided to the drain of the second MOS transistor of the second conductivity type.

3. An output circuit according to claim 2 , wherein the first cascode circuit and the second cascode circuit each comprise a depletion mode MOS transistor of the second conductivity type including a gate connected to the second power supply terminal.

4. An output circuit according to claim 1 , further comprising:

a first impedance element provided to the drain of the first MOS transistor of the second conductivity type; and

a second impedance element provided to the drain of the third MOS transistor of the second conductivity type.

5. An output circuit according to claim 1 , wherein:

the current mirror circuit further comprises a fifth MOS transistor of the first conductivity type;

the fifth MOS transistor of the first conductivity type includes a gate connected to the gate of the third MOS transistor of the first conductivity type and a drain connected to the drain of the third MOS transistor of the second conductivity type; and

the fifth MOS transistor of the first conductivity type mirrors a current corresponding to a difference between the current of the first current source and the drain current of the second MOS transistor of the first conductivity type.

Assignments (4)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2012
From: TOMIOKA, TSUTOMU
To: SEIKO INSTRUMENTS INC.
Reel/Frame 027577/0023 →