Programmable signal processing circuit and method of interleaving

1. A method of interleaving a signal, the method comprising:

extracting data from the signal;

storing the extracted data in a data memory and reading the stored extracted data from the data memory after said storing;

computing addresses, for use in said storing and/or reading, from preceding addresses that have been used for said storing and/or reading, by means of repeated execution of a program loop that contains an address update instruction for computing the addresses, the address update instruction defining locations of an old address operand and a new address result, the new address result being formed in response to at least part of the executions of the address update instruction by permuting positions of a plurality of bits from the old address operand and forming of a bit of the new address result as a logic function of a combination of bits from the old address operand.

2. The method according to claim 1 , comprising

determining, in response to each execution of the address update instruction, whether a number represented by the new address result operand exceeds a threshold value;

writing a flag result that indicates whether the number represented by the new address result operand exceeds a threshold value, to a flag location that is addressed by the address update instruction; and

using the flag result from the flag location to condition execution of a further instruction in said loop that uses the new address result as operand.

3. The method according to claim 1 , comprising

starting repeated cycles, each of a same series of addresses for use in said storing and/or reading, during execution of the program loop implicitly in response to execution of the address update instruction by deviating from said permuting and forming of the bit to form the new address result when the old address operand has a predetermined value.

4. The method according to claim 1 comprising receiving data for a DVB signal and interleaving the data into a DVB signal.

5. A programmable signal processing circuit, comprising:

an operand storage circuit;

an instruction processing circuit, for executing instructions that address locations of operands and results in the operand storage circuit, an instruction set of the instruction processing circuit comprising an address update instruction, the instruction processing circuit comprising:

an operand input for receiving an old address operand of the address update instruction from the operand storage circuit,

a result output for writing a new address result of the address update instruction to the operand storage circuit,

a permutation circuit coupled between the operand input and the result output and arranged to control values of a plurality of bits at respective output bit positions in the new address result dependent on respective bits from respective input positions that are a permutation of the output bit positions,

a combinatorial logic circuit coupled between the operand input and the result output, with the combinatorial logic circuit having inputs coupled to receive bits from respective input bit positions in the old address operand and an output coupled to output a bit to a bit position in the new address result,

a comparator circuit with an input coupled to the operand input and an output, and

a bit substitution circuit coupled in series with the permutation circuit, with a control input coupled to the output of the comparator circuit and arranged to substitute a predetermined bit value at one of said plurality of output positions when the comparator circuit indicates that the old address operand contains a predetermined combination of bit values; and

an addressable memory;

wherein the programmable signal processing circuit is programmed with a program to interleave received data, the program containing a call of the address update instruction in a program loop, the program loop containing a load and/or store instruction that addresses the new address results from said call as memory access operands to determine addresses of memory locations in the addressable memory.