Continuous read burst support at high clock rates
View Patent ↗A memory device includes a memory array, an output buffer, an initial latency register, and an output signal. Often times a host device that interfaces with the memory device is clocked at high rate such that data extraction rates of the memory device are not adequate to support a gapless data transfer. The output signal is operable to stall a transmission between the memory device and the host device when data extraction rates from the memory array are not adequate to support output rates of the output buffer.
1. A memory device, comprising:
a memory array operable for storing data;
an initial latency register operable for storing a preselected latency time; and
an output buffer coupled to said memory array, wherein said output buffer stores said data prior to a transmission of said data to a host device, wherein said memory device outputs a signal to stall said transmission until said data has been stored in said output buffer, and wherein the transmission is stalled while the output signal is idle.
2. The memory device of claim 1 , wherein said data comprises an initial page of data and subsequent pages of data.
3. The memory device of claim 2 , wherein said memory device is a non-volatile memory device.
4. The memory device of claim 1 , wherein said latency time corresponds to the number of clock cycles required to extract a page of data from said memory array and store said page of data in said output buffer.
5. The memory device of claim 1 , wherein said output signal remains idle for a number of clock cycles after said transmission of said data to said host device.
6. The memory device of claim 5 , wherein said number of clock cycles is dependent on a number of clock cycles required for said transmission of said data to said host device and said latency time.
7. The memory device of claim 5 , wherein said number of clock cycles is dependent on a number of clock cycles required for said transmission of said data to said host device, said latency time, and a starting address for said transmission of said data to said host device.
8. The memory device of claim 1 , wherein said output signal toggles at a predetermined frequency during said transmission of said data to said host device.
9. The memory device of claim 1 , wherein said transmission to said host device occurs via a data bus, said data bus operating at a frequency faster than said memory array outputs said data.
10. The memory device of claim 1 , wherein said output signal is a read data strobe.
11. An apparatus, comprising:
a memory device operable to support continuous read bursts to a host device wherein an output signal stalls a transmission from the memory device as defined by a preselected length of time, and wherein the transmission is stalled while the output signal is idle;
a bus interface providing connectivity between said memory device and said host device; and
a processor.
12. The apparatus of claim 11 , wherein said memory device further comprises:
a memory array operable for storing data; and
an output buffer coupled to said memory array, wherein said output buffer stores said data prior to a transmission of said data to said host device, wherein said output signal stalls said transmission until said data has been stored in said output buffer.
13. The apparatus of claim 12 , wherein:
said output signal remains idle for a number of clock cycles after said transmission of said data to said host device; and
said output signal toggles at a predetermined frequency during said transmission of said data to said host device.
14. The apparatus of claim 12 , wherein said transmission occurs via said bus interface, said bus interface operating at a frequency faster than said memory array outputs said data.
15. A method, comprising:
requesting data from a memory device on a computer system, wherein said memory device comprises an initial latency register storing a preselected latency time;
retrieving a page or partial page of said data from an array within said memory device;
holding an output signal idle until page or partial page of data is stored into an output buffer and placed on a data bus; and
toggling said output signal while transmitting said page or partial page of data to a host device to indicate to said host device that said page or partial page of data is available on said data bus, and wherein the data transmission is stalled while the output signal is idle.
16. The method of claim 15 , wherein said latency time corresponds to the number of clock cycles required to extract said page of data from said memory array and store said page of data in said output buffer.
17. The method of claim 15 , wherein said holding further comprises said output signal remaining idle for a number of clock cycles after said transmission of said data to said host device.
18. The method of claim 17 , wherein said number of clock cycles is dependent on a number of clock cycles required for said transmission of said data to said host device and said latency time.
19. The method of claim 17 , wherein said number of clock cycles is dependent upon a number of clock cycles required for said transmission of said data to said host device, said latency time, and a starting address for said transmission of said data to said host device.
20. The method of claim 15 , wherein said toggling further comprises toggling said output signal at a predetermined frequency during said transmission of said data to said host device.