Method for forming a semiconductor layer with improved gap filling properties
View Patent ↗A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.
1. A method of manufacturing a memory device, the method comprising:
forming a dielectric layer over a substrate;
forming a charge storage element over the dielectric layer;
etching the charge storage element;
forming an inter-gate dielectric over the dielectric layer and the etched charge storage element;
depositing a polysilicon layer over the inter-gate dielectric, where depositing the polysilicon control gate layer includes:
providing a first reactant to a deposition chamber, and
providing a second reactant to the deposition chamber;
planarizing the polysilicon layer to form a control gate;
forming an interlayer dielectric on the control gate;
planarizing the interlayer dielectric;
forming, after forming the control gate and planarizing the interlayer dielectric, a contact hole through the planarized interlayer dielectric and the control gate;
depositing a metal layer to fill the contact hole, the metal layer including a first type of metal; and
forming an interconnect over the planarized interlayer dielectric, the interconnect including a second type of metal.
2. The method of claim 1 , where the inter-gate dielectric includes a plurality of layers, and the plurality of layers include a nitride layer and at least one oxide layer.
3. The method of claim 1 , where, when etching the charge storage element, the method further comprising:
etching the charge storage element to create a plurality of structures.
4. The method of claim 1 , where the polysilicon layer is planarized using chemical-mechanical polishing.
5. The method of claim 1 , where a top surface of the interlayer dielectric is planarized using chemical-mechanical polishing.
6. The method of claim 1 , where the first type of metal is one of tungsten, copper, or aluminum.
7. The method of claim 1 , where the contact hole forms a contact to a source region or a drain region.
8. A method of manufacturing a memory device, the method comprising:
forming a dielectric layer over a substrate;
forming a charge storage element over the dielectric layer;
etching the charge storage element;
forming an inter-gate dielectric over the dielectric layer and the etched charge storage element;
depositing a polysilicon layer over the inter-gate dielectric, where depositing the polysilicon control gate layer includes;
providing a first reactant to a deposition chamber, and
providing a second reactant to the deposition chamber,
where the first reactant and the second reactant are concurrently provided to the deposition chamber;
planarizing the polysilicon layer to form a control gate;
forming an interlayer dielectric on the control gate;
planarizing the interlayer dielectric;
forming, after forming the control gate and planarizing the interlayer dielectric, a contact hole through the planarized interlayer dielectric and the control gate;
depositing a metal layer to fill the contact hole, the metal layer including a first type of metal; and
forming an interconnect over the planarized interlayer dielectric, the interconnect including a second type of metal.
9. The method of claim 8 , where the inter-gate dielectric includes a plurality of layers, and the plurality of layers include a nitride layer and at least one oxide layer.
10. The method of claim 8 , where, when etching the charge storage element, the method further comprising:
etching the charge storage element to create a plurality of structures.
11. The method of claim 8 , where the polysilicon layer is planarized using chemical-mechanical polishing.
12. The method of claim 8 , where a top surface of the interlayer dielectric is planarized using chemical-mechanical polishing.
13. The method of claim 8 , where the first type of metal is one of tungsten, copper, or aluminum.
14. The method of claim 8 , where the contact hole forms a contact to a source region or a drain region.
15. A method of manufacturing a memory device, the method comprising:
forming a dielectric layer over a substrate;
forming a charge storage element over the dielectric layer;
etching the charge storage element;
forming an inter-gate dielectric over the dielectric layer and the etched charge storage element;
depositing a polysilicon layer over the inter-gate dielectric, where depositing the polysilicon control gate layer includes:
providing a SiH 2 Cl 2 reactant to a deposition chamber, and
providing a SiH 4 reactant to the deposition chamber;
planarizing the polysilicon layer to form a control gate;
forming an interlayer dielectric on the control gate;
planarizing the interlayer dielectric;
forming, after forming the control gate and planarizing the interlayer dielectric, a contact hole through the planarized interlayer dielectric and the control gate;
depositing a metal layer to fill the contact hole, the metal layer including a first type of metal; and
forming an interconnect over the planarized interlayer dielectric, the interconnect including a second type of metal.
16. The method of claim 15 , where the inter-gate dielectric includes a plurality of layers, and the plurality of layers include a nitride layer and at least one oxide layer.
17. The method of claim 15 , where, when etching the charge storage element, the method further comprising:
etching the charge storage element to create a plurality of structures.
18. The method of claim 15 , where the polysilicon layer is planarized using chemical-mechanical polishing.
19. The method of claim 15 , where a top surface of the interlayer dielectric is planarized using chemical-mechanical polishing.
20. The method of claim 15 , where the contact hole forms a contact to a source region or a drain region.