Rasterizer packet generator for use in graphics processor
View Patent ↗A rasterizer in a graphic processor device implemented on a field programmable gate array circuitry (FPGA). The rasterizer comprises a preprocessor that creates data packets to generate at least one line, a main module that generates a stream of data fragments that become pixels, and a postprocessor that combines the data fragments and pipeline commands into one output to a fragment processor.
1. A rasterizer in a graphic processor device implemented on a field programmable gate array circuitry, comprising:
a preprocessor that receives commands and vertices and creates data packets to generate at least one line;
a main module that generates a stream of data fragments that become pixels, wherein the main module further comprises a multi-threading packet processing engine that determines a dominant axis having a larger change in value in the line and sequences the vertices so that vertex coordinates increase along the dominant axis; and
a postprocessor that combines the data fragments and pipeline commands into one output to a fragment processor.
2. The rasterizer of claim 1 , wherein the multi-threading packet processing engine further comprises:
an input event module that parses incoming data packets and prepares them for processing.
3. The rasterizer of claim 1 , wherein the multi-threading packet processing engine further comprises:
a setup event module that calculates all gradients for the incoming data packets.
4. The rasterizer of claim 1 , wherein the multi-threading packet processing engine further comprises:
a draw event module performs actual fragment generation for the incoming data packets.
5. The rasterizer of claim 1 , wherein the multi-threading packet processing engine further comprises:
a thread packet processing unit (TPU).
6. The rasterizer of claim 5 , wherein the TPU further comprises:
a PreSetup_Event process that executes in the TPU and decodes command bits to determine how to interpret vertex data.
7. The rasterizer of claim 5 , wherein the TPU further comprises:
a Setup_Event process that executes in the TPU and determines if the line generation is for a line or triangle edge.
8. The rasterizer of claim 5 , wherein the TPU further comprises:
a Kill_Packet process that deallocates the data packet's memory.
9. A hardware description language (HDL) design structure encoded on a non-transitory machine-readable data storage medium, the HDL design structure comprising elements that when executed in a computer-aided design system generate a machine-executable representation of a rasterizer in a graphic processor device implemented on a field programmable gate array circuitry, wherein the HDL design structure comprises:
a preprocessor module that, when executed, receives commands and vertices and creates data packets to generate at least one line;
a main module that, when executed, generates a stream of data fragments that become pixels, wherein the main module further comprises a multi-threading packet processing module that, when executed, determines a dominant axis having a larger change in value in the line and sequences the vertices so that vertex coordinates increase along the dominant axis; and
a postprocessor module that, when executed, combines the data fragments and pipeline commands into one output to a fragment processor.
10. The HDL design structure of claim 9 , wherein the HDL design structure further comprises:
a plurality of buffer modules that, when executed, allow for storage while downstream modules are continuing to process previous data.
11. The HDL design structure of claim 9 , wherein the multi-threading packet processing engine module further comprises:
an input event module that, when executed, parses incoming data packets and prepares them for processing;
a setup event module that, when executed, calculates all gradients for the incoming data packets; and
a draw event module that, when executed, performs actual fragment generation for the incoming data packets.
12. The HDL design structure of claim 9 , wherein the multi-threading packet processing module further comprises:
a thread packet processing unit (TPU) module.
13. The HDL design structure of claim 9 , wherein the TPU further comprises:
a PreSetup_Event process that, when executed, decodes command bits to determine how to interpret vertex data;
a Setup_Event process that, when executed, determines if the line generation is for a line or triangle edge; and
a Kill_Packet process that, when executed, deallocates the data packet's memory.
14. The HDL design structure of claim 9 , wherein the HDL design structure comprises a netlist.
15. The HDL design structure of claim 9 , wherein the HDL design structure resides in a field programmable gate array.
16. An improved rasterizer for use in a graphic processor device implemented on a field programmable gate array (FPGA) circuitry, the improvement therein comprising:
that the FPGA rasterizer includes a preprocessor that receives commands and vertices and creates data packets to generate at least one line;
the FPGA rasterizer further includes a main module that generates a stream of data fragments that become pixels, wherein the main module further comprises a multi-threading packet processing engine that determines a dominant axis having a larger change in value in the line and sequences the vertices so that vertex coordinates increase along the dominant axis; and
wherein the FPGA rasterizer further includes a postprocessor that combines the data fragments and pipeline commands into one output to a fragment processor.