Programmable queuing instruction set
View Patent ↗A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.
1. A device comprising:
a scheduler configured to schedule queues of data in a payload memory, based on at least one of: priority, rate and bandwidth guarantee; and
an execution unit comprising decode logic configured to decode instructions from an instruction set, wherein the instruction set comprises:
an operation code to write data to the payload memory but not enqueue the data; and
another operation code to reorganize the data held in payload memory to a queue.
2. The device of claim 1 wherein:
the execution unit comprises a pipeline, the decode logic is included in an early stage of the pipeline, and the memory bus is coupled to a last stage of the pipeline; and
the execution unit further comprises a first-in-first-out memory coupled to an input bus of the pipeline.
3. The device of claim 1 further comprising:
an input bus coupled to the execution unit to supply thereto the data and the instructions; and
a network processor coupled to the input bus, the network processor comprising a processing unit programmed to identify a queue number and generate at least one instruction for each unit of data to be transmitted on the input bus, the processing unit in the network processor comprising another decode logic different from said decode logic of the execution unit;
wherein the execution unit and the scheduler are included in a traffic manager, the traffic manager being coupled to the network processor by the input bus.
4. The device of claim 3 wherein the traffic manager further comprises a pointer pool, said pointer pool being coupled to each of said network processor and said execution unit.
5. The device of claim 1 wherein the instruction set further comprises yet another instruction to set up a sequence in which the data is read from the payload memory but without moving the data in payload memory.
6. An instruction set enabled in a non-transitory memory, wherein the instruction set comprises an operation code to:
write data to a non-transitory memory but not link the data to a queue in the memory;
set up an order in which the data is read from the memory but without moving the data addresses in the non-transitory memory; and
link data held in the non-transitory memory to the queue.
7. The instruction set of claim 6 further comprising:
the data to be written, if the instruction is to write the data to the non-transitory memory.
8. The instruction set of claim 6 further comprising:
a pointer to be used in executing the operation code.
9. The instruction set of claim 8 traveling on a bus located wholly inside a single integrated circuit (IC) die.
10. A method for forming queues in a memory, the method comprising:
receiving a write instruction, a queue number, and a unit of data from a bus;
decoding the write instruction;
executing the write instruction, by storing the unit of data in the memory;
receiving a stitch instruction;
decoding the stitch instruction;
executing the stitch instruction, by changing at least one pointer to the unit of data in the memory;
receiving a link instruction;
decoding the link instruction; and
executing the link instruction, by coupling the units of data of the packet to the queue.
11. The method of claim 10 wherein said receiving, decoding, executing and repeating are performed in a first circuit, the first circuit being coupled by the bus to a second circuit, and the method further comprises the second circuit:
receiving the unit of data and a header from another bus;
analyzing the header to identify the queue number;
creating the write instruction;
sending the unit of data, the queue number, and the write instruction to the first circuit; and
repeating said receiving, analyzing, creating and sending until all units of data of a packet are received and thereafter creating and sending the stitch instruction and the link instruction to the first circuit.
12. The method of claim 10 further comprising:
receiving an additional write instruction from said bus;
decoding the additional write instruction; and
storing the unit of data in the memory and linking the unit of data to the queue, during execution of the additional write instruction.