Thin film transistor array panel and manufacturing method thereof
View Patent ↗A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.
1. A thin film transistor array panel comprising: a gate electrode disposed on a substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed on the gate insulating layer4Nith the same layer ; a source electrode and a drain electrode disposed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer, wherein the entirety of both the first electrode and the second electrode are disposed in one pixel area defined by two data lines and two gate lines [of the substrate] and are completely spaced apart from one another by the passivation layer.
2. The thin film transistor array panel of claim 1 , further comprising an etch stopper disposed on the oxide semiconductor.
3. The thin film transistor array panel of claim 2 , wherein the first electrode and a portion of the oxide semiconductor that is not covered by the etch stopper comprise hydrogen plasma-treated surfaces.
4. The thin film transistor array panel of claim 3 , wherein the oxide semiconductor comprises indium-gallium-zinc oxide.
5. The thin film transistor array panel of claim 4 , wherein:
the first electrode and the oxide semiconductor are disposed directly on the gate insulating layer; and
the second electrode is formed directly on the passivation layer and does not overlap with the first electrode in a direction perpendicular to the plane of the substrate.
6. The thin film transistor array panel of claim 1 , wherein the first electrode and the second electrode are sub-pixel electrodes applied with data voltages.
7. The thin film transistor array panel of claim 1 , wherein the first electrode and the second electrode are applied with data voltages having different magnitudes and that are obtained from one image signal.
8. The thin film transistor array panel of claim 4 , wherein:
the first electrode is a pixel electrode; and
the second electrode is a reference electrode.
9. The thin film transistor array panel of claim 8 , wherein:
the first electrode is applied with a data voltage; and
the second electrode is applied with a reference voltage.
10. The thin film transistor array panel of claim 1 , wherein portions of the oxide semiconductor and the first electrode comprise hydrogen plasma-treated surfaces.
11. The thin film transistor array panel of claim 10 , wherein the oxide semiconductor comprises indium-gallium-zinc oxide
12. The thin film transistor array panel of claim 11 , wherein the first electrode and the second electrode are sub-pixel electrodes.
13. The thin film transistor array panel of claim 12 , wherein the first electrode and the second electrode are applied with data voltages.
14. The thin film transistor array panel of claim 13 , wherein the first electrode and the second electrode are applied with data voltages having different magnitudes and are obtained from one image signal.
15. The thin film transistor array panel of claim 11 , wherein:
the first electrode is a pixel electrode; and
the second electrode is a reference electrode.
16. The thin film transistor array panel of claim 15 , wherein:
the first electrode is applied with a data voltage; and
the second electrode is applied with a reference voltage.
17. The thin film transistor array panel of claim 1 , wherein the oxide semiconductor and the first electrode comprise indium-gallium-zinc oxide.
18. The thin film transistor array panel of claim 17 , wherein the first electrode and the second electrode are sub-pixel electrodes.
19. The thin film transistor array panel of claim 18 , wherein the first electrode and the second electrode are applied with data voltages.
20. The thin film transistor array panel of claim 19 , wherein the data voltages of the first electrode and the second electrode have different magnitudes and are obtained from one image signal.
21. The thin film transistor array panel of claim 18 , wherein:
the first electrode is a pixel electrode; and
the second electrode is a reference electrode.
22. The thin film transistor array panel of claim 21 , wherein:
the first electrode is applied with a data voltage; and
the second electrode is applied with a reference voltage.
23. The thin film transistor array panel of claim 1 , wherein the first electrode and the second electrode are sub-pixel electrodes.
24. The thin film transistor array panel of claim 23 , wherein the first electrode and the second electrode are applied with data voltages.
25. The thin film transistor array panel of claim 24 , wherein the data voltages of the first electrode and the second electrode have different magnitudes and are obtained from one image signal.
26. The thin film transistor array panel of claim 1 , wherein:
the first electrode is a pixel electrode; and
the second electrode is a reference electrode.
27. The thin film transistor array panel of claim 26 , wherein:
the first electrode is applied with a data voltage; and
the second electrode is applied with a reference voltage.
28. A method for manufacturing a thin film transistor array panel, comprising: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming an oxide semiconductor and a first electrode on the gate insulating layer, by patterning an oxide semiconductor material layer; forming a source electrode and a drain electrode on the oxide semiconductor; forming a passivation layer on the first electrode, the source electrode, and the drain electrode; and forming a second electrode on the passivation layer, wherein the entirety of both the first electrode and the second electrode are disposed in one pixel area defined by two data lines and two gate lines [of the substrate] and are completely spaced apart from one another by the passivation layer.
29. The method of claim 28 , further comprising:
forming an etch stopper on the oxide semiconductor; and
treating a portion of the oxide semiconductor that is not covered by the etch stopper and is not covered by the first electrode with hydrogen plasma.
30. The method of claim 29 , wherein: the oxide semiconductor comprises indium-gallium-zinc oxide.
31. The method of claim 30 , wherein the first electrode and the second electrode are sub-pixel electrodes.
32. The method of claim 30 , wherein:
the first electrode is a pixel electrode; and
the second electrode is a reference electrode.
33. The method of claim 28 , wherein the oxide semiconductor comprises indium-gallium-zinc oxide.
34. The method of claim 28 , wherein: the oxide semiconductor and the first electrode are formed directly on the gate insulating layer; and
the second electrode is formed directly on the passivation layer and does not overlap with the first electrode in a direction perpendicular to the plane of the substrate.
35. The method of claim 33 , wherein:
the first electrode is a pixel electrode; and
the second electrode is a reference electrode.
36. The method of claim 28 , wherein the first electrode and the second electrode are sub-pixel electrodes.
37. The method of claim 28 , wherein:
the first electrode is a pixel electrode; and
the second electrode is a reference electrode.