Identifying and correcting a bit error in a FRAM storage unit of a semiconductor device

1. A semiconductor device comprising a control unit and an FRAM storage unit having FRAM cells comprising a predetermined test data pattern, wherein the control unit is configured to:

read the FRAM cells in a margin-mode that are dedicated to the test data of the test data pattern,

compare the read out bit information with the predetermined test data pattern to determine whether a bit error is present in the dedicated FRAM cells and when a bit error is present in the dedicated FRAM cells:

read-out the complete FRAM storage unit in a recovery-mode and

refresh all FRAM cells of the FRAM storage unit by writing back the read out bit information to the respective FRAM cells, wherein in the margin-mode, the read operation is performed using a lower read-sensitivity compared to the read operation reading out the complete FRAM storage unit that is performed in the recovery-mode.

2. The semiconductor device of claim 1 , wherein in the margin-mode, a sense voltage is applied to the FRAM cells comprising the test data pattern so as to lower a bit cell signal of the respective FRAM cells.

3. The semiconductor device of claim 2 , wherein the FRAM cells of the FRAM storage unit comprise a sense amplifier for providing a bit line signal and the sense voltage is applied to the sense amplifier so as to lower a level of the bit cell output signal provided to the bit line.

4. The semiconductor device of claim 1 , wherein a predetermined set of parameters is used for a standard read-out operation of the FRAM-cells, and wherein for the read operation of the complete FRAM storage in the recovery-mode a further set of parameters is applied so as to provide a read process providing a bit-cell signal having a higher signal margin in comparison to the bit-cell signal in a read operation using the set of parameters for the standard read-out.

5. The semiconductor device of claim 4 , wherein the further set of parameters causes a timing of the bit-cell signals to slow down and/or a plate line to provide a higher voltage to the FRAM cells, in comparison to the standard read-out operation.

6. The semiconductor device according to claim 5 , wherein the control unit is further configured to perform the write back operation using the further set of parameters.

7. The semiconductor device of claim 1 , wherein the control unit is further configured to perform a bit-error correction before writing back the read out bit information.

8. A method for identifying and correcting a bit error in an FRAM storage unit of a semiconductor device, the FRAM storage unit having a plurality of FRAM cells comprising a predetermined test data pattern, the method comprising the steps of:

reading the FRAM cells that are dedicated to the test data pattern in a margin-mode,

comparing the read-out bit information with the predetermined test data pattern to determine whether a bit error is present in the dedicated FRAM cells and if so:

reading-out the complete FRAM storage unit in a recovery-mode and

refreshing all FRAM cells of the FRAM storage unit by writing back the read out bit information, wherein in the margin mode, the read operation is performed using a lower read-sensitivity compared to the read operation of the complete FRAM storage unit that is performed in the recovery-mode.