Thin film transistor array panel and manufacturing method thereof

1. A thin film transistor array panel, comprising:

a gate wiring layer disposed on a substrate;

an oxide semiconductor layer disposed on the gate wiring layer; and

a data wiring layer disposed on the oxide semiconductor layer, wherein:

the data wiring layer comprises a main wiring layer and an outermost capping layer in direct contact with an upper surface of the main wiring layer, the main wiring layer being disposed between the outermost capping layer and the oxide semiconductor layer; the main wiring layer comprises copper and the capping layer comprises a metallic copper alloy;

a continuous thickness of the main wiring layer is greater than a continuous thickness of the capping layer; and

a lateral side wall of the main wiring layer aligns substantially flush with an edge of a lateral side wall of the capping layer.

2. The thin film transistor array panel of claim 1 , wherein the metallic copper alloy comprises at least one of vanadium (V), titanium (Ti), zirconium (Zr), tantalum (Ta), manganese (Mn), magnesium (Mg), chromium (Cr), molybdenum (Mo), cobalt (Co), niobium (Nb), and nickel (Ni).

3. The thin film transistor array panel of claim 2 , wherein the metallic copper alloy comprises a metallic copper-manganese alloy.

4. The thin film transistor array panel of claim 3 , wherein the oxide semiconductor layer comprises at least one of zinc (Zn), indium (In), tin (Sn), gallium (Ga), and hafnium (Hf).

5. The thin film transistor array panel of claim 1 , wherein the data wiring layer further comprises a barrier layer disposed below the main wiring layer.

6. The thin film transistor array panel of claim 5 , wherein the barrier layer comprises a material made of an alloy of at least one of vanadium (V), zirconium (Zr), tantalum (Ta), manganese (Mn), magnesium (Mg), chromium (Cr), molybdenum (Mo), cobalt (Co), niobium (Nb), nickel (Ni), and copper (Cu).

7. The thin film transistor array panel of claim 6 , wherein the material forming the alloy with copper of the barrier layer has the content of about 10 at % or more.

8. The thin film transistor array panel of claim 1 , wherein the data wiring layer comprises a data line, a source electrode, and a drain electrode facing the source electrode, the data line crossing the gate line.

9. The thin film transistor array panel of claim 8 , further comprising:

a passivation layer covering the data line and the drain electrode and comprising a contact hole exposing a part of the drain electrode; and

a pixel electrode electrically connected with the drain electrode through the contact hole.

10. The thin film transistor array panel of claim 9 , wherein the passivation layer comprises silicon oxide.