Apparatus and method for a dual mode standard and layered belief propagation LDPC decoder

1. An apparatus for a dual mode low density parity check (LDPC) decoder comprising:

edge random access memory (RAM);

last-in-first-out/first-in-first-out (LIFO/FIFO) RAM;

channel RAM; and

a plurality of parallel data path engines, wherein the datapath engines comprise a standard belief propagation decoding (SBD) datapath and a layered belief propagation decoding (LBD) datapath, wherein the SBD datapath comprises a shifter, an accumulator, a plurality of multiplexers, and a g′( )_sbd calculator, and wherein the LBD datapath comprises the shifter, the plurality of multiplexers, and a g′( )_lbd calculator.

2. The apparatus of claim 1 , wherein the LDPC decoder is implemented in one Very-Large-Scale-Integration (VLSI) hardware module.

3. The apparatus of claim 1 , wherein the LDPC decoder is configured to perform SBD using the SBD datapath in a first mode, and LBD using the LBD datapath in a second mode.

4. The apparatus of claim 3 , wherein in the first mode the plurality of multiplexers activate the accumulator and g( )_sbd calculator of the SBD datapath and deactivate the g′( )_lbd calculator.

5. The apparatus of claim 3 , wherein in the second mode the plurality of multiplexer activate the g′( )_lbd calculator and deactivate the accumulator and the g( )sbd calculator.

6. The apparatus of claim 1 , further comprising:

microcode read-only-memory (ROM);

microcode RAM;

decision RAM; and

a controller comprising an SBD controller and an LBD controller.

7. The apparatus of claim 6 , wherein the controller selects between a first mode of the LDPC decoder and a second mode of the LDPC decoder, and wherein the LDPC decoder performs SBD using the SBD datapath in the first mode, and LBD using the LBD datapath in the second mode.

8. The apparatus of claim 1 , wherein the LDPC decoder is implemented on one application specific integrated circuit (ASIC).

9. The apparatus of claim 1 , wherein the LDPC decoder is implemented on one field programmable gate array (FPGA).

10. The apparatus of claim 1 , wherein the SBD datapath and the LBD datapath share the edge RAM, the channel RAM, and the LIFO/FIFO RAM.

11. The apparatus of claim 1 , wherein the shifter is shared between the SBD datapath and the LBD datapath and is in between inputs and outputs of the dual mode LDPC decoder.

12. The apparatus of claim 1 , wherein components of the LBD datapath and the SBD datapath are controlled by microcodes.

13. A method for a dual mode LDPC decoder comprising:

receiving a signal indicating a first mode of operation or a second mode operation; and

activating the first mode of operation or the second mode of operation based on the signal,

wherein the first mode of operation is standard belief propagation decoding (SBD) and the second mode of operation is layered belief propagation decoding (LBD), and

wherein activating the first mode of operation activates an SBD datapath comprising SBD specific components and shared components, and deactivates LBD specific components.

14. The method of claim 13 , wherein activating the second mode of operation activates an LBD datapath comprising LBD specific components and shared components and deactivates SBD specific components.

15. The method of claim 14 , wherein activating the LBD specific components and the shared components further comprises:

activating a g′( )_lbd calculator;

activating a shifter;

activating an edge RAM;

activating a channel RAM; and

activating a LIFO/FIFO RAM in a FIFO mode.

16. The method of claim 14 , further comprising controlling the LBD specific components with microcodes from a microcode RAM.

17. The method of claim 14 , wherein activating the SBD specific components and the shared components further comprises:

activating an accumulator;

activating a g ( )_sbd calculator;

activating a shifter;

activating an edge RAM;

activating a channel RAM; and

activating a LIFO/FIFO RAM in a LIFO mode.

18. The method of claim 13 , further comprising controlling the SBD specific components with microcodes from a microcode RAM.

19. A method for a dual mode LDPC decoder comprising:

receiving a signal indicating a first mode of operation or a second mode operation; and

activating the first mode of operation or the second mode of operation based on the signal,

wherein the first mode of operation is standard belief propagation decoding (SBD) and the second mode of operation is layered belief propagation decoding (LBD), and

wherein activating the first mode of operation or the second mode of operation further comprises applying a signal to a plurality of multiplexers based on the receiving signal indicating the first mode of operation or the second mode of operation.