IP Library Granted Patent US 8,750,660
Granted Patent B2
US 8,750,660 · App. 13/369,324 · Granted Jun 10, 2014

Integrated optical interconnect

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Quick Facts
Patent No.
US 8,750,660
App. No.
13/369,324
Granted
Jun 10, 2014
Kind
B2
Abstract

A method for fabricating an integrated optical interconnect includes disposing a layer over a substrate on which at least one optoelectronic transducer has been formed. A groove is formed in the layer in alignment with the optoelectronic transducer. A slanted mirror is formed in the layer at an end of the groove adjacent to the optoelectronic transducer to direct light between the optoelectronic transducer and an optical fiber placed in the groove.

Claims (31)

1. A method for fabricating an integrated optical interconnect, the method comprising:

disposing a layer over a semiconductor wafer substrate on which a plurality of optoelectronic transducers have been formed;

forming respective grooves in the layer in alignment with a plurality of the optoelectronic transducers;

forming a slanted mirror in the layer at an end of each groove adjacent to the respective optoelectronic transducer to direct light between the optoelectronic transducer and an optical fiber placed in the groove; and

dicing the semiconductor wafer, after disposing the layer and forming the grooves and slanted mirrors, to create multiple engine dies, each including one or more optoelectronic transducers and respective grooves and mirrors.

2. The method according to claim 1 , wherein disposing the layer comprises disposing a Gallium Arsenide (GaAs) layer.

3. The method according to claim 2 , wherein disposing the layer comprises fabricating the layer using GaAs fabrication process that is also used for forming the optoelectronic transducer.

4. The method according to claim 1 , and comprising testing the optoelectronic transducer prior to dicing the wafer.

5. The method according to claim 1 , wherein the optoelectronic transducers comprise vertical cavity surface emitting lasers (VCSELs).

6. The method according to claim 1 , wherein the optoelectronic transducers comprise photodetectors.

7. The method according to claim 1 , wherein disposing the layer comprises disposing a polymer layer.

8. The method according to claim 1 , wherein forming the slanted mirror comprises cutting the layer at a bevel.

9. The method according to claim 1 , wherein forming the slanted mirror comprises disposing a lens on a surface of each slanted mirror, prior to dicing the semiconductor wafer.

10. An integrated optical interconnect, comprising:

a semiconductor wafer substrate on which a plurality of optoelectronic transducers have been formed; and

a layer disposed on the semiconductor wafer substrate, the layer including:

grooves, which are formed in the layer in alignment with respective optoelectronic transducers, for placing optical fibers; and

respective slanted mirrors, which are formed in the layer at ends of the grooves, adjacent to the respective optoelectronic transducers, so as to direct light between the respective optoelectronic transducers and the optical fibers placed in the grooves,

wherein the layer is bonded to or epitaxially grown on the semiconductor wafer substrate.

11. The optical interconnect according to claim 10 , wherein the layer comprises a Gallium Arsenide (GaAs) layer.

12. The optical interconnect according to claim 11 , wherein the layer is fabricated using a GaAs fabrication process that is also used for forming the optoelectronic transducer.

13. The optical interconnect according to claim 10 , wherein the optoelectronic transducers comprise vertical cavity surface emitting lasers (VCSELs).

14. The optical interconnect according to claim 10 , wherein the optoelectronic transducers comprise photodetectors.

15. The optical interconnect according to claim 10 , wherein the layer comprises a polymer layer.

16. The optical interconnect according to claim 10 , and comprising lenses disposed on a surface of each of the slanted mirrors.

17. The method according to claim 1 , wherein the optoelectronic transducers comprise both VCSELs and photodetectors.

18. The method according to claim 1 , wherein disposing the layer comprises bonding the layer to the substrate.

19. The method according to claim 1 , wherein disposing the layer comprises epitaxially growing the layer onto the substrate.

20. The method according to claim 8 , wherein cutting the layer at a bevel comprises cutting by an etching process.

21. The method according to claim 8 , wherein cutting the layer at a bevel comprises cutting by a mechanical saw.

22. The method according to claim 1 , wherein forming the slanted mirror comprises disposing a thin layer of gold on a surface of each slanted mirror, prior to dicing the semiconductor wafer.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 37900/0720 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 046542/0792 →
PATENT SECURITY AGREEMENT Recorded Feb 24, 2016
From: MELLANOX TECHNOLOGIES, LTD.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 037900/0720 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2012
From: LEVY, SHMUEL; COHEN, SHAI; REPHAELI, SHAI; BABISH, EYAL; LOVINGER, RONNEN
To: MELLANOX TECHNOLOGIES LTD.
Reel/Frame 027675/0724 →