IP Library Granted Patent US 8,375,281
Granted Patent B2
US 8,375,281 · App. 13/369,624 · Granted Feb 12, 2013

Method and apparatus for storing survivor paths in a viterbi detector using systematic pointer exchange

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Quick Facts
Patent No.
US 8,375,281
App. No.
13/369,624
Granted
Feb 12, 2013
Kind
B2
Abstract

A survivor path memory is provided for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state. The input processor generates a control signal that exchanges one or more pointers based on a trellis structure, wherein each of the pointers points to one of the flip flops.

Claims (12)

1. A survivor path memory for a Viterbi detector, comprising:

a plurality of columns, each of said columns associated with a different time step, each of said columns comprising:

a memory element for storing one bit or portion of a bit sequence associated with a Viterbi state, each of said memory elements having at least one data input; and

a switch for each state controlled by a case signal indicating a time step, said switch selecting a state from a previous time step, wherein an output of said switch of a given state is connected to said at least one data input of a memory element of said given state; and

an input processor for generating a control signal that exchanges one or more pointers based on a trellis structure, wherein each of said pointers points to one of said memory elements.

2. The survivor path memory of claim 1 , wherein one or more of said states maintain values and wherein said associated pointers are maintained in said associated memory elements.

3. The survivor path memory of claim 1 , wherein one or more of said memory elements are updated based on a value of a write enable signal.

4. The survivor path memory of claim 1 , wherein an output of each of said memory elements is stored in a corresponding buffer, and wherein said buffer contents are read based on a value of a read enable signal.

5. The survivor path memory of claim 1 , wherein one or more of said memory elements are updated based on a value provided by an input processor.

6. The survivor path memory of claim 1 , wherein said trellis structure comprises one or more butterfly trellises.

7. The survivor path memory of claim 1 , wherein said trellis structure has been collapsed to combine a plurality of steps into a single step.

8. The survivor path memory of claim 1 , wherein one or more of said states do not change values and wherein said associated pointers are not updated by said one or more predefined rules.

Assignments (6)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
CERTIFICATE OF CONVERSION Recorded Nov 5, 2012
From: GRAEF, NILS
To: AGERE SYSTEMS LLC
Reel/Frame 029244/0609 →