State responsive operations relating to flash memory cells
A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state.
1. A method for state responsive operations relating to flash memory cells, the method comprises:
encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and
programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state;
wherein for a low wear level of the flash memory cells the encoding comprises using short codewords and the programming comprises applying analog equalization.
2. The method according to claim 1 , wherein an aggregate duration of the encoding and the programming is inversely proportional to a reliability level associated with the state.
3. The method according to claim 1 , comprising selecting a length of each codeword in response to the state.
4. The method according to claim 3 , wherein the length of each codeword is proportional to a wear level of the flash memory cells.
5. The method according to claim 1 , comprising selecting an interleaving scheme to be applied during the state responsive programming process in response to the state.
6. The method according to claim 5 , comprising selecting between a non-interleaving option, an inter-flash memory die interleaving option and an intra-flash memory die option in response to the state.
7. The method according to claim 5 , comprising selecting a number of partitions of the each codeword to be interleaved based upon the state.
8. The method according to claim 1 , comprising selecting a threshold voltage distribution affecting scheme in response to the state.
9. The method according to claim 8 , comprising selecting an analog equalization parameter.
10. The method according to claim 1 , wherein for a high wear level of the flash memory cells, the programming comprises applying interleaving and does not comprise applying analog equalization.
11. The method according to claim 10 , wherein the programming comprises applying programming parameters that result in nearly equal bit error rate for each read threshold regardless of a type of programming.
12. The method according to claim 11 , wherein the encoding comprises using a different encoding scheme for each page type of programming.
13. The method according to claim 1 , comprising performing partial decoding.
14. The method according to claim 1 , comprising changing sizes of payloads and of redundancy information as a response of the state of the flash memory cells while maintaining in relation to the flash memory cells a substantially constant ratio between an aggregate size of stored information and an aggregate size of redundancy information.
15. The method according to claim 1 , wherein the flash memory cells comprise multiple sets of flash memory cells and wherein the method comprises applying the encoding of a portion of the information entity based upon a state of a set of flash memory cells that is expected to store the portion of the information entity.
16. The method according to claim 1 , wherein the flash memory cells comprise multiple sets of flash memory cells and wherein the method comprises applying the programming of a portion of the information entity based upon a state of a set of flash memory cells that is expected to store the portion of the information entity.
17. The method according to claim 1 , wherein the encoding comprises increasing a size of redundancy information with an increase of a wear level of the flash memory cells.
18. The method according to claim 1 , comprising performing state responsive buffering in response to the state of the flash memory cells.
19. A method for state responsive operations relating to flash memory cells, the method comprises:
encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells;
programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state;
selecting an interleaving scheme to be applied during the state responsive programming process in response to the state; and
selecting between
programming different portions of a same codeword by a same type of programming, and
programming different portions of the same codeword by different types of programming;
wherein the different types of programming comprise at least two out of most significant bit (MSB) programming, central significant bit (CSB) programming and least significant bit (LSB) programming.
20. A method for state responsive operations relating to flash memory cells, the method comprises:
encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells;
programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state;
selecting a threshold voltage distribution affecting scheme in response to the state; and
selecting a threshold voltage distribution affecting parameter out of a start program value, a program voltage step size and a program voltage step window.
21. The method according to claim 20 , wherein for a low wear level of the flash memory cells the encoding comprises using short codewords and the programming comprises applying analog equalization.
22. A non-transitory computer readable medium that stores instructions for:
encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and
programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state; the state being either an estimated state or an actual state;
wherein for a low wear level of the flash memory cells the encoding comprises using short codewords and the programming comprises applying analog equalization.
23. A flash memory controller, comprising:
an encoding circuit configured to encode an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and
a programming circuit configured to program the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state; the state being either an estimated state or an actual state;
wherein for a low wear level of the flash memory cells the encoding comprises using short codewords and the programming comprises applying analog equalization.
24. A method for state responsive programming, the method comprises programming at least one codeword to at least one group of flash memory cells by applying at least two state responsive programming operations, each state responsive programming operation is responsive to a state of flash memory cells; and selecting between (a) programming different portions of a same codeword by a same type of programming, and (b) programming different portions of the same codeword by different types of programming, wherein the different types of programming comprise at least two out of most significant bit (MSB) programming, central significant bit (CSB) programming and least significant bit (LSB) programming.
25. The method according to claim 24 , comprising selecting in response to the state of the flash memory cells at least one out of a start program value, a program voltage step size and a program voltage step window.