Obtaining soft information using a hard interface
View Patent ↗A flash memory controller, a computer readable medium and a method for generating reliability information using a hard information interface, the method may include performing multiple read attempts, while using the hard information interface, of a plurality of flash memory cells to provide multiple read results; wherein each flash memory cell is read by providing a reference voltage to the flash memory cell; wherein a same reference voltage is provided during the multiple read attempts; and generating, for each flash memory cell, reliability information based upon multiple read results of the flash memory cell.
1. A method for generating reliability information using a hard information interface, the method comprising:
performing multiple read attempts, while using the hard information interface, of a plurality of flash memory cells to provide multiple read results; wherein each flash memory cell is read by providing a reference voltage to the flash memory cell; wherein a same reference voltage is provided during the multiple read attempts; and
generating, for each flash memory cell, reliability information based upon multiple read results of the flash memory cell.
2. The method according to claim 1 , comprising generating the reliability information of a flash memory cell based upon (a) a relationship between numbers of read result of different values of the flash memory cells, and (b) a first mapping between values of the relationship and reliability information values.
3. The method according to claim 2 , wherein the generating of the reliability information is further responsive to a state of the multiple flash memory cells.
4. The method according to claim 1 , comprising selecting a value of information representative of a content of a flash memory cell based upon (a) a relationship between numbers of read result of different values of the flash memory cells, and (b) a first mapping between values of the relationship and values of information representative of the content of the flash memory cell.
5. The method according to claim 4 , comprising generating the reliability information of the flash memory cell based upon (a) the relationship between numbers of read result of different values of the flash memory cells, and (b) the first mapping between values of the relationship and reliability information values.
6. The method according to claim 1 comprising:
estimating, for each flash memory cell, a voltage difference between a threshold voltage of the flash memory cell and the reference voltage provided; and
wherein the generating, for each flash memory cell, the reliability information is responsive to the voltage difference of the flash memory cell.
7. The method according to claim 6 , comprising using same read parameters during the multiple read attempts.
8. The method according to claim 6 , wherein the estimating of the voltage difference of each flash memory cell is responsive to (a) relationship between numbers of read result of different values and (b) a second mapping between the relationship and the voltage difference.
9. The method according to claim 8 , comprising estimating the second mapping based upon a state of the multiple flash memory cells.
10. The method according to claim 8 , comprising estimating the second mapping based upon a wear level of the multiple flash memory cells.
11. The method according to claim 8 , comprising estimating the second mapping based upon an evaluated retention of the multiple flash memory cells.
12. The method according to claim 6 , comprising performing different types of read attempts that differ from each other by bit significance; wherein the estimating of the voltage difference of each flash memory cell is responsive to read results obtained during all of the types of the read attempts.
13. The method according to claim 6 , comprising generating reliability information that is a log likelihood ratio (LLR).
14. The method according to claim 1 , comprising supplying a supply voltage of different values to the multiple flash memory cells during different read attempts.
15. The method according to claim 14 , comprising estimating, for each flash memory cell, a flipping supply voltage that causes a change in a value of a read result of the flash memory cell.
16. The method according to claim 15 , wherein the estimating of the voltage difference of a flash memory cell comprises: calculating a supply voltage difference between the flipping supply voltage value and a reference value of the supply voltage; and estimating the voltage difference based upon the supply voltage difference and a third mapping between supply voltage difference values and voltage difference values.
17. The method according to claim 16 , wherein the reference value is selected out of the different values of the supply voltage.
18. The method according to claim 15 , comprising finding, for each of the different values of the supply voltages, a number of flipping flash memory cells; and selecting a reference value of the supply voltage based upon the numbers of flipping flash memory cells.
19. The method according to claim 18 , comprising finding the reference voltage within a range of supply voltages that is exhibits a minimal change in a number of flipping flash memory cells.
20. The method according to claim 1 , comprising performing the multiple read attempts without being aware of exact values of read thresholds utilized to read the multiple flash memory cells.
21. The method according to claim 1 , comprising performing the multiple read attempts while being prevented from directly changing read thresholds utilized to read the multiple flash memory cells.
22. The method according to claim 1 , comprising calculating a first mapping between values of the relationship and reliability information values by programming known information to a plurality of flash memory cells; reading the plurality of flash memory cells multiple times to provide test results and comparing the test results to the known information.
23. The method according to claim 1 , comprising generating the reliability information of a flash memory cell based upon (a) a relationship between numbers of read result of different values of the flash memory cells, (b) and a mapping between the relationship and log likelihood ratio (LLR).
24. The method according to claim 23 comprising calculating the mapping between the relationship and the LLR by programming and reading known information.
25. The method according to claim 1 , comprising selecting a value of information representative of a content of a flash memory cell based upon a relationship between numbers of read result of different values of the flash memory cells.
26. The method according to claim 25 , comprising selecting a value of information representative of a content of a flash memory cell based upon (a) a ratio between numbers of read result of different values of the flash memory cells; and (b) mapping between values of the ratio and values of the information.
27. The method according to claim 1 , comprising generating a value of information representative of a content of a flash memory cell by performing a logical operation on multiple read results of a same flash memory cell.
28. The method according to claim 1 , comprising selecting a value of information representative of a certain bit of a content of a flash memory cell based upon a value of information representative of at least one more significant bit of the content of the flash memory cell.
29. The method according to claim 28 , comprising:
selecting a selected logical operation to be applied on multiple read results of a same flash memory cell; and
applying the selected logical operation on the multiple read results to provide a value of information representative of the certain bit of the content of the flash memory cell;
wherein the selecting of the selected logical operation is responsive to the value of information representative of the at least one more significant bit of the content of the flash memory cell.
30. The method according to claim 28 , comprising:
selecting a selected operand out of a “larger than” operand and a “smaller than” operand;
comparing between a ratio between numbers of read result of different values of the flash memory cells and a threshold using the selected operand to provide a value of information representative of a certain bit of a content of a flash memory cell;
wherein the selecting is responsive to the value of information representative of the at least one more significant bit of the content of the flash memory cell.
31. A non-transitory computer readable medium that stores instructions for: performing multiple read attempts while using the hard information interface, of a plurality of flash memory cells to provide multiple read results; wherein each flash memory cell is read by providing a reference voltage to the flash memory cell; wherein a same reference voltage is provided during the multiple read attempts; and generating, for each flash memory cell, reliability information based upon multiple read results of the flash memory cell.
32. A flash memory controller, comprising: (a) an interface arranged to send read commands to a flash memory device and to receive from a hard interface of a flash memory device read results indicative of a content of multiple flash memory cells of the flash memory device; wherein each flash memory cell is read by providing a reference voltage to the flash memory cell; wherein a same reference voltage is provided during the multiple read attempts; and (b) a reliability module arranged to generate, for each flash memory cell, reliability information based upon multiple read results of the flash memory cell.