Disk drive comprising a dual read element and delay circuitry to improve read signal
View Patent ↗A disk drive is disclosed comprising a disk having a plurality of data tracks, and a head actuated over the disk, the head comprising a first read element and a second read element. A data track is read to generate a first read signal emanating from the first read element and a second read signal emanating from the second read element. The first read signal is delayed in continuous time relative to the second read signal to generate a delayed read signal, and the second read signal is combined with the delayed read signal to generate a combined read signal. An estimated data sequence is detected from the combined read signal.
1. A disk drive comprising:
a disk comprising a plurality of data tracks;
a head actuated over the disk, the head comprising a first read element and a second read element; and
control circuitry operable to:
read a data track to generate a first read signal emanating from the first read element and a second read signal emanating from the second read element;
sample the second read signal using a clock to generate second sample values;
synchronize the clock in response to the second sample values;
delay the clock;
sample the first read signal using the delayed clock to generate first sample values representing the delayed read signal; and
combine the first sample values with the second sample values to generate a combined read signal; and
detect an estimated data sequence from the combined read signal.
2. The disk drive as recited in claim 1 , wherein the control circuitry is further operable to:
detect a phase error in response to the first sample values; and
adjust the delay of the clock in response to the phase error.
3. A method of operating a disk drive, the disk drive comprising a disk comprising a plurality of data tracks, and a head actuated over the disk, the head comprising a first read element and a second read element, the method comprising:
reading a data track to generate a first read signal emanating from the first read element and a second read signal emanating from the second read element;
sampling the second read signal using a clock to generate second sample values;
synchronizing the clock in response to the second sample values;
delaying the clock;
sampling the first read signal using the delayed clock to generate first sample values representing the delayed read signal; and
combining the first sample values with the second sample values to generate a combined read signal; and
detecting an estimated data sequence from the combined read signal.
4. The method as recited in claim 3 , further comprising:
detecting a phase error in response to the first sample values; and
adjusting the delay of the clock in response to the phase error.