Integrated circuit nanowires
View Patent ↗Implementations of encapsulated nanowires are disclosed.
1. An integrated circuit, comprising:
a first buffer circuit;
a second buffer circuit;
a nanowire communicatively coupling the first buffer circuit to the second buffer circuit; and
an insulating material disposed over the nanowire,
wherein the insulating material has a thickness of less than 5 nm.
2. The integrated circuit of claim 1 , wherein the nanowire comprises copper, aluminum, tungsten or any combination thereof.
3. The integrated circuit of claim 1 , wherein the insulating material comprises silicon dioxide.
4. The integrated circuit of claim 1 , further comprising:
a logic module including the first buffer circuit,
wherein the logic module is configured to convey a high frequency signal from the first buffer circuit to the second buffer circuit via the nanowire.
5. The integrated circuit of claim 4 , wherein the high frequency signal comprises a clock signal.
6. The integrated circuit of claim 4 , wherein the logic module comprises clock signal generation logic.
7. An integrated circuit, comprising:
a first buffer circuit;
a second buffer circuit;
a first nanowire;
a second nanowire;
the first nanowire and second nanowire configured to convey a fully-differential signal to communicatively couple the first buffer circuit to the second buffer circuit; and
an insulating material disposed over the first nanowire and second nanowire,
wherein the insulating material has a thickness of less than 5 nm.
8. The integrated circuit of claim 7 , wherein the first nanowire comprise copper, aluminum, tungsten or any combination thereof.
9. The integrated circuit of claim 7 , wherein the insulating material comprises silicon dioxide.
10. The integrated circuit of claim 7 further comprising:
a logic module including the first buffer circuit,
wherein the logic module is configured to convey a high frequency signal from the first buffer circuit to the second buffer circuit via the first and second nanowires.
11. The integrated circuit of claim 10 , wherein the high frequency signal comprises a clock signal.
12. The integrated circuit of claim 10 , wherein the logic module comprises clock signal generation logic.
13. An integrated circuit, comprising:
a first buffer circuit;
a second buffer circuit;
a nanowire communicatively coupling the first buffer circuit to the second buffer circuit; and
one or more insulating monolayers of silicon dioxide disposed over the nanowire to entirely encapsulate the nanowire,
wherein each of the one or more insulating monolayers of silicon dioxide has a thickness of less than 0.5 nm.
14. The integrated circuit of claim 13 , wherein the nanowire comprises copper, aluminum, tungsten or any combination thereof.
15. The integrated circuit of claim 13 further comprising:
a logic module including the first buffer circuit,
wherein the logic module is configured to convey a high frequency signal from the first buffer circuit to the second buffer circuit via the nanowire.
16. The integrated circuit of claim 15 , wherein the high frequency signal comprises a clock signal.
17. The integrated circuit of claim 16 , wherein the logic module comprises clock signal generation logic.