Thin film transistor array panel for liquid crystal display having pixel electrode overlaping data and gate lines with different widths and areas
View Patent ↗A TFT array panel includes an insulating substrate, a gate line, a storage electrode line, a gate insulating layer, a semiconductor island formed on the gate insulating layer, and a data line and a drain electrode formed thereon. The data line and drain electrode are covered with a passivation layer. A pixel electrode is formed on the passivation layer and connected to the drain electrode through a contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode overlaps the gate line and data line and has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or data line.
1. A method for manufacturing a thin film transistor array panel comprising:
forming a gate line on a substrate, the gate line comprising a gate electrode;
disposing a semiconductor and a data wire sequentially on the substrate;
patterning the semiconductor and the data wire, wherein the data wire comprises a first data line, a second data line, a source electrode and a drain electrode, the second data line is spaced apart from the first data line, the drain electrode faces a part of the first data line and the second data line, and the source electrode is connected to one of the first data line and the second data line;
forming an organic insulating layer on the first data line and the second data line, the organic insulating layer having a contact hole exposing the drain electrode; and
forming a pixel electrode on the organic insulating layer, the pixel electrode electrically connected to the drain electrode;
wherein the pixel electrode comprises a first part overlapping the first data line, and a second part overlapping the second data line, and
wherein the width of the first part is different from that of the second part.
2. The method of claim 1 , further comprising disposing an ohmic contact between the semiconductor and the data line, and wherein the ohmic contact is patterned with the semiconductor and the data wire.
3. The method of claim 2 , wherein the pixel electrode comprises a third part and a fourth part respectively overlapping the gate line, and wherein the width of the fourth part is greater than that of the third part.
4. The method of claim 3 , wherein the fourth part has different widths.
5. The method of claim 1 , wherein the pixel electrode is connected to the drain electrode through the contact hole.
6. The method of claim 5 , further comprising forming a storage electrode making a storage conductor with the pixel electrode.
7. The method of claim 6 , further comprising forming a storage electrode line on the substrate.
8. A method for manufacturing a thin film transistor array panel comprising:
forming a first gate line and a second gate line formed on a substrate, wherein the first gate line is separated from the second gate line, and comprises a gate electrode;
disposing a semiconductor and a data wire sequentially on the substrate;
patterning the semiconductor and the data wire, wherein the data wire comprises a data line, a source electrode and a drain electrode, the drain electrode faces a part of the data line, and the source electrode is connected to the data line;
forming an organic insulating layer on the data line, the organic insulating layer having a contact hole exposing the drain electrode; and
forming a pixel electrode on the organic insulating layer, the pixel electrode electrically connected to the drain electrode;
wherein the pixel electrode comprises a first part overlapping the first gate line, and a second part overlapping the second gate line, and
wherein the width of the first part is different from that of the second part.
9. The method of claim 8 , wherein the first overlapping area has different widths.
10. The method of claim 9 , further comprising disposing an ohmic contact between the semiconductor and the data line, and wherein the ohmic contact is patterned with the semiconductor and the data wire.
11. The method of claim 9 , wherein the pixel electrode is connected to the drain electrode through the contact hole.
12. The method of claim 11 , further comprising forming a storage electrode making a storage conductor with the pixel electrode.
13. The method of claim 12 , further comprising forming a storage electrode line on the substrate.