IP Library Granted Patent US 9,620,478
Granted Patent B2
US 9,620,478 · App. 13/372,292 · Granted Apr 11, 2017

Method of fabricating a micro device transfer head

Inventors: Andreas Bibl (Los Altos, CA); John A. Higginson (Santa Clara, CA); Hung-Fai Stephen Law (Los Altos, CA); Hsin-Hua Hu (Los Altos, CA)
Assignee: Apple Inc.
H01L24/83H01L21/67144H01L21/6833H01L24/75H01L24/95H01L24/97B32B37/025B32B37/06B32B2457/20H01L2224/7598H01L2224/75725H01L2224/83005H01L2224/97H01L2924/10253H01L2924/10329H01L2924/12041H01L2924/1421H01L2924/1431H01L2924/1434H01L2924/1461H01L2924/15153Y10T156/1153Y10T156/1707Y10T156/1744Y10T156/1749Y10T156/1776
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Quick Facts
Patent No.
US 9,620,478
App. No.
13/372,292
Granted
Apr 11, 2017
Kind
B2
Abstract

A micro device transfer head and head array are disclosed. In an embodiment, the micro device transfer head includes a base substrate, a mesa structure with sidewalls, an electrode formed over the mesa structure, and a dielectric layer covering the electrode. A voltage can be applied to the micro device transfer head and head array to pick up a micro device from a carrier substrate and release the micro device onto a receiving substrate.

Claims (32)

1. A method of fabricating an array of electrostatic transfer heads comprising:

forming an array of mesa structures on a base substrate, each mesa structure including sidewalls;

forming a passivation layer over the base substrate and the array of mesa structures, wherein forming the passivation over the base substrate and the array of mesa structures comprises a technique selected from the group consisting of conformal deposition of the passivation layer over the base substrate and the array of mesa structures and growing the passivation layer over the base substrate and the array of mesa structures;

forming a separate electrode directly on the passivation layer and over each corresponding mesa structure such that each electrode is electrically insulated from each corresponding mesa structure; and

depositing a dielectric layer over the array of mesa structures and each electrode.

2. The method of claim 1 , wherein depositing the dielectric layer comprises atomic layer deposition.

3. The method of claim 1 , wherein forming the separate electrodes directly on the passivation and over each corresponding mesa structure comprises forming a pair of electrodes over each corresponding mesa structure, wherein each electrode in each pair of electrodes are electrically insulated from each other, and depositing the dielectric layer over the array of mesa structures and each electrode comprises depositing the dielectric layer over each pair of electrodes.

4. The method of claim 3 , further comprising forming a conductive ground plane over the dielectric layer and surrounding each of the mesa structures, wherein the conductive ground plane includes an array of openings surrounding the array of mesa structures, and each mesa structure protrudes through a corresponding opening in the conductive ground plane.

5. The method of claim 1 , wherein forming the passivation over the base substrate and the array of mesa structures comprises conformal deposition of the passivation layer over the base substrate and the array of mesa structures.

6. The method of claim 1 , wherein forming the passivation over the base substrate and the array of mesa structures comprises growing the passivation layer over the base substrate and the array of mesa structures.

7. The method of claim 1 , wherein forming the array of mesa structures comprises etching an oxide layer formed over a semiconductor substrate.

8. The method of claim 1 , wherein depositing the dielectric layer comprises depositing multiple dielectric layers.

9. The method of claim 1 , wherein the array of mesa structures are integrally formed with the base substrate.

10. The method of claim 1 , wherein each electrode comprises a material selected from the group consisting of platinum, titanium, vanadium, chromium, zirconium, niobium, molybdenum, ruthenium, rhodium, hafnium, tantalum, tungsten, rhenium, osmium, iridium and alloys thereof.

11. The method of claim 1 , wherein each electrode comprises TiW.

12. The method of claim 1 , wherein the dielectric layer comprises a dielectric material selected from the group consisting of Al 2 O 3 and Ta 2 O 5 .

13. A method of fabricating an array of electrostatic transfer heads comprising:

forming an array of mesa structures on a base substrate, each mesa structure including sidewalls;

forming a pair of electrodes over each corresponding mesa structure, wherein the electrodes in each pair of electrodes are electrically insulated from each other; and

depositing a dielectric layer over the array of mesa structures and each electrode;

wherein a top surface of the dielectric layer over each mesa structure corresponds to a contact surface for a corresponding electrostatic transfer head in the array of electrostatic transfer heads.

14. The method of claim 13 , further comprising forming a pair of electrode leads, wherein each electrode lead runs from a corresponding electrode over a top surface of the corresponding mesa structure along a sidewall of the corresponding mesa structure.

15. The method of claim 13 , wherein the pair of electrodes are separated by 0.5 μm or less.

16. The method of claim 13 , wherein forming the pair of electrodes over each corresponding mesa structure comprises a lift off technique.

17. The method of claim 13 , wherein forming the pair of electrodes over each corresponding mesa structure comprises metal layer deposition and etching of the metal layer.

18. A method of fabricating an array of electrostatic transfer heads comprising:

forming an array of mesa structures on a base substrate, each mesa structure including sidewalls;

forming a separate electrode over each corresponding mesa structure;

depositing a dielectric layer over the array of mesa structures and each electrode; and

forming a conductive ground plane over the dielectric layer and surrounding each of the mesa structures, wherein the conductive ground plane includes an array of openings surrounding the array of mesa structures, and each mesa structure protrudes through a corresponding opening in the conductive ground plane.

19. The method of claim 18 , wherein the conductive ground plane has a same or lower melting temperature than the separate electrodes.

20. The method of claim 18 , wherein the array of mesa structures are integrally formed with the base substrate.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2016
From: LUXVUE TECHNOLOGY CORPORATION
To: APPLE INC.
Reel/Frame 038521/0255 →
RELEASE OF SECURITY INTEREST Recorded May 2, 2014
From: COMERICA BANK
To: LUXVUE TECHNOLOGY CORPORATION
Reel/Frame 032812/0733 →
SECURITY AGREEMENT Recorded May 20, 2013
From: LUXVUE TECHNOLOGY CORPORATION
To: TRIPLEPOINT CAPITAL LLC
Reel/Frame 030450/0558 →
SECURITY AGREEMENT Recorded Mar 21, 2013
From: LUXVUE TECHNOLOGY CORPORATION
To: COMERICA BANK
Reel/Frame 030058/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2012
From: BIBL, ANDREAS; HIGGINSON, JOHN A.; LAW, HUNG-FAI STEPHEN; HU, HSIN-HUA
To: LUXVUE TECHNOLOGY CORPORATION
Reel/Frame 027697/0018 →
Continuity (4)
Provisional Application 61561706 · Nov 18, 2011
Provisional Application 61594919 · Feb 3, 2012
Provisional Application 61597109 · Feb 9, 2012
Related Publication 20130130416A1 · May 23, 2013