Manufacturing of electronic components
View Patent ↗According to an aspect of the invention, a method is provided for manufacturing electronic components. A conducting element comprising a first portion, a second portion and a third portion between the first portion and the second portion is provided. Thermally responsive dielectric material is added at least onto the third portion of the conducting element. Electric current is supplied between the first portion and the second portion of the conducting element causing ohmic heating to affix dielectric material located on the third portion to the third portion. Non-thermally-affixed dielectric material is removed.
1. A method for manufacturing electronic components, comprising:
providing a conducting element comprising a first portion, a second portion and a third portion between the first portion and the second portion, wherein the cross-sectional area of the third portion is less than the cross-sectional area of the first portion and the cross-sectional area of the second portion,
adding thermally responsive dielectric material at least onto the third portion of the conducting element,
supplying electric current between the first portion and the second portion of the conducting element causing ohmic heating to affix dielectric material located on the third portion to the third portion, and
removing non-thermally-affixed dielectric material.
2. The method of claim 1 , wherein the cross-sectional area of the third portion is less than the cross-sectional area of the first portion and the cross-sectional area of the second portion.
3. The method of claim 1 , wherein the thermally responsive material is thermally cross-linkable and the affixing of thermally responsive material is provided by cross-linking.
4. The method of claim 1 , wherein the conducting element is provided for forming a field-effect transistor structure, and the thermally affixed dielectric forms a gate channel dielectric.
5. The method of claim 4 , wherein a source, a drain, and the gate are formed substantially on the same level on top of a substrate.
6. The method of claim 4 , wherein the source, the drain and the gate are formed by one of: ink-jet, gravure, flexography, screen, offset, pad or micro-contact printing, nano-imprint lithography, wet etching, photolithography, or laser ablation.
7. The method of claim 4 , wherein the source, the drain and the gate are separated by an embossing operation.
8. The method of claim 7 , wherein an input material comprising a compressible layer and a conductive layer on the compressible layer is provided, and
a single embossing operation is performed on the conductive layer to separate the gate by at least two embossed lines.
9. The method of claim 1 , wherein the dielectric material is low-temperature cross-linkable dielectric material selected from a group comprising: polymethylmethacrylate PMMA, polyvinylchloride PVC, polyamide PI, polyethylene PE, polyvinylalcohol PVA, cyanoethylpullulan CYPEL, polystyrene PS, poly(4-vinylphenol) PVP.