IP Library Patent Application 13383726
Patent Application
App. No. 13/383,726

DIFFERENTIAL SIGNAL TRANSMISSION LINE, IC PACKAGE, AND METHOD FOR TESTING SAID DIFFERENTIAL SIGNAL TRANSMISSION LINE AND IC PACKAGE

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Patent No.
US None
App. No.
13/383,726
Abstract

An IC package includes an integrated circuit for transmitting and receiving a pair of differential signals composed of a signal having positive polarity and a signal having negative polarity, a first signal terminal for transmitting the signal having positive polarity, a second signal terminal for transmitting the signal having negative polarity, and a third terminal arranged between the first signal terminal and the second signal terminal. The first and second terminals are electrically connected to the integrated circuit, and the third terminal is not electrically connected to the integrated circuit.

Claims (45)

1 . An IC package comprising:

an integrated circuit for transmitting and receiving a pair of differential signals composed of a signal having positive polarity and a signal having negative polarity;

a first signal terminal for transmitting the signal having positive polarity;

a second signal terminal for transmitting the signal having negative polarity; and

a third terminal arranged between the first signal terminal and the second signal terminal, wherein

the first and second terminals are electrically connected to the integrated circuit, and

the third terminal is not electrically connected to the integrated circuit.

2 . The IC package according to claim 1 , wherein the third terminal is a terminal connected to a reference potential.

3 . The IC package according to claim 1 , wherein a plurality of the third terminals are provided.

4 . The IC package according to claim 1 , wherein

the first and second signal terminals and the third terminal have a portion that appears outside the IC package and a portion extending inside the IC package, respectively,

the portion of the third terminal extending inside the IC package is arranged on a position that is equally separated from the portion of the first signal terminal extending inside the IC package and the portion of the second signal terminal extending inside the IC package.

5 . The IC package according to claim 1 , further comprising first and second ground terminals connected to a reference potential,

wherein the first and second signal terminal and the third terminal are arranged between the first ground terminal and the second ground terminal.

6 . A differential signal transmission line for transmitting a pair of differential signals composed of a signal having positive polarity and a signal having negative polarity, the differential signal transmission line comprising:

a first signal terminal for transmitting the signal having positive polarity;

a second signal terminal for transmitting the signal having negative polarity; and

a third terminal that is arranged between the first signal terminal and the second signal terminal and is not connected to any electric potential.

7 . The differential signal transmission line according to claim 6 , further comprising first and second ground terminals connected to a reference potential,

wherein the first and second signal terminals and the third terminal are arranged between the first ground terminal and the second ground terminal.

8 . The differential signal transmission line according to claim 6 , wherein the third terminal is used as a test terminal in a predetermined performance test on the differential signal transmission line.

9 . An IC package comprising the differential signal transmission line of claim 6 .

10 . A connector comprising the differential signal transmission line of claim 6 .

11 . A testing method of the differential signal transmission line of claim 8 , comprising:

applying a noise signal for the test to the third terminal; and

evaluating a receiving performance when applying the noise signal to the third terminal to evaluate common mode noise immunity based on a measured signal.

12 . A testing method of the differential signal transmission line of claim 8 , comprising:

applying ESD to the third terminal; and

evaluating a receiving performance when applying the ESD to the third terminal to evaluate ESD immunity based on a measured signal.

13 . A testing method of the differential signal transmission line of claim 8 , comprising:

connecting the third terminal to a ground potential via a resistor;

applying the differential signals to the first and second signal terminals,

measuring a voltage generated at the resistor connected to the third terminal; and

evaluating skew of differential signals based on the measured voltage.

14 . A testing method of the IC package of claim 1 , comprising:

applying a noise signal for a test to the third terminal; and

evaluating a receiving performance when applying the noise signal to the third terminal, thereby evaluating common mode noise immunity based on a measured signal.

15 . A testing method of the IC package of claim 1 , comprising:

applying ESD to the third terminal; and

evaluating a receiving performance when applying the ESD to the third terminal, thereby evaluating ESD immunity based on a measured signal.

16 . A testing method of the IC package of claim 1 , comprising:

connecting the third terminal to a ground potential via a resistor;

applying differential signals for a test to the first and second signal terminals;

measuring a voltage generated at the resistor connected to the third terminal; and

evaluating skew of the differential signals based on a measured voltage.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2012
From: MASUDA, KOHEI; SHIBATA, OSAMU; SUENAGA, HIROSHI; SAITO, YOSHIYUKI
To: PANASONIC CORPORATION
Reel/Frame 028100/0744 →