IP Library Granted Patent US 9,041,491
Granted Patent B2
US 9,041,491 · App. 13/384,719 · Granted May 26, 2015

Capacitive device and resonance circuit

Inventors: Noritaka Sato (Kanagawa, JP); Masayoshi Kanno (Kanagawa, JP); Masakazu Yajima (Kanagawa, JP)
Assignee: DEXERIALS CORPORATION
H01G4/30H03H2001/0085H01G4/012H01G4/232H03H7/0115
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Quick Facts
Patent No.
US 9,041,491
App. No.
13/384,719
Granted
May 26, 2015
Kind
B2
Abstract

To provide a capacitive device capable of accurately securing a capacitance value, a variable capacitive device capable of sufficiently securing a capacity variability rate, and a resonance circuit that uses the capacitive devices. A capacitive device includes a capacitive device body constituted of a dielectric layer and at least a pair of capacitive device electrodes that sandwich the dielectric layer and cause a desired electric field in the dielectric layer; and stress adjustment portions to adjust a stress caused in the dielectric layer of the capacitive device body.

Claims (31)

1. A resonance circuit, comprising:

a resonance capacitor comprising a capacitive device that comprises

a capacitive device body comprising a dielectric layer and at least a pair of capacitive device electrodes that sandwich the dielectric layer and cause a desired electric field in the dielectric layer,

a stress adjustment portion that adjusts a stress caused in the dielectric layer of the capacitive device body, wherein the stress adjustment portion comprises a stress adjustment dielectric layer and a plurality of stress adjustment electrodes laminated in the stress adjustment dielectric layer;

at least a first pair of external electrodes connected to the at least a pair of capacitive device electrodes; and

at least a second pair of external electrodes connected to the plurality of stress adjustment electrodes; and

a resonance coil connected to the resonance capacitor.

2. A capacitive device, comprising:

a capacitive device body comprising a dielectric layer and at least a pair of capacitive device electrodes that sandwich the dielectric layer and cause a desired electric field in the dielectric layer;

a stress adjustment portion to adjust a stress caused in the dielectric layer of the capacitive device body, wherein the stress adjustment portion comprises a stress adjustment dielectric layer and a plurality of stress adjustment electrodes laminated in the stress adjustment dielectric layer;

at least a first pair of external electrodes connected to the at least a pair of capacitive device electrodes; and

at least a second pair of external electrodes connected to the plurality of stress adjustment electrodes.

3. The capacitive device according to claim 2 ,

wherein the stress adjustment portion is laminated in a thickness direction of the dielectric layer of the capacitive device body.

4. The capacitive device according to claim 3 ,

wherein the stress adjustment portion sandwiches the capacitive device body.

5. The capacitive device according to claim 4 ,

wherein the at least a pair of capacitive device electrodes and the plurality of stress adjustment electrodes are in parallel, and

wherein a stress adjustment voltage is applied to the plurality of stress adjustment electrodes.

6. The capacitive device according to claim 5 , wherein the stress adjustment voltage comprises antipolar voltages;

the plurality of stress adjustment electrodes to which the antipolar voltages are applied are arranged alternately in the stress adjustment portion.

7. The capacitive device according to claim 6 ,

wherein the dielectric layer is formed of a ferroelectric material having a capacity that changes based on a control voltage, and the control voltage is applied between the pair of capacitive device electrodes.

8. The capacitive device according to claim 7 ,

wherein the stress adjustment voltage is larger than the control voltage.

9. The capacitive device according to claim 2 ,

wherein the plurality of stress adjustment electrodes are electrically connected to the at least a pair of capacitive device electrodes.

10. The capacitive device according to claim 2 ,

wherein the plurality of stress adjustment electrodes float electrically.

11. The capacitive device according claim 2 ,

wherein a plurality of the at least a pair of capacitive device electrodes are laminated via the dielectric layer in the capacitive device body.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2012
From: SONY CHEMICAL & INFORMATION DEVICE CORPORATION
To: DEXERIALS CORPORATION
Reel/Frame 029348/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2012
From: SONY CORPORATION
To: SONY CHEMICAL & INFORMATION DEVICE CORPORATION
Reel/Frame 029207/0984 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2012
From: SATO, NORITAKA; KANNO, MASAYOSHI; YAJIMA, MASAKAZU
To: SONY CORPORATION
Reel/Frame 027584/0828 →
Priority Claims (2)
JP 2009-175919 · Jul 28, 2009 · national
JP 2010-100378 · Apr 23, 2010 · national
Continuity (1)
Related Publication 20120112855A1 · May 10, 2012