Dual use transistor
View Patent ↗A circuit for amplifying radio frequency signals comprising: a terminal for connection to an antenna; a common amplifier arranged in a common-gate configuration between a first node and said terminal; a transmit amplifier operable to amplify a radio frequency signal present at an input node and provide the amplified signal to said first node; and a receive amplifier operable to amplify a radio frequency signal present at said first node and provide the amplified signal to an output node; wherein the circuit is operable in two modes: in a receive mode, the common and receive amplifiers being configured so as to together form a receive cascode for amplifying radio frequency signals received at the terminal; and in a transmit mode, the common and transmit amplifiers being configured so as to together form a transmit cascode for amplifying radio frequency signals applied at the input node.
1. A circuit for amplifying radio frequency signals comprising:
a terminal for connection to an antenna;
a common amplifier arranged in a common-gate configuration between a first node and said terminal;
a transmit amplifier operable to amplify a radio frequency signal present at an input node and provide the amplified signal to said first node; and
a receive amplifier operable to amplify a radio frequency signal present at said first node and provide the amplified signal to an output node;
wherein the circuit is operable in two modes:
in a receive mode, the common and receive amplifiers being configured so as to together form a receive cascode for amplifying radio frequency signals received at the terminal; and
in a transmit mode, the common and transmit amplifiers being configured so as to together form a transmit cascode for amplifying radio frequency signals applied at the input node and wherein a common gate voltage applied to the gate of the common amplifier is modified so as to modulate the amplitude of a transmitted signal in accordance with a predetermined amplitude modulation scheme.
2. A circuit as claimed in claim 1 , wherein in receive mode the transmit amplifier is off.
3. A circuit as claimed in claim 1 , wherein in transmit mode the receive amplifier is off.
4. A circuit as claimed in claim 1 , further comprising voltage biasing means coupled to said terminal and operable to regulate the DC voltage at the terminal, the voltage biasing means being configured to:
in the receive mode, set the DC voltage at the terminal such that the common amplifier is arranged to amplify signals received at the antenna;
in the transmit mode, set the DC voltage at the terminal such that the common amplifier is arranged to amplify signals received from the transmit amplifier.
5. A circuit as claimed in claim 4 , wherein the DC voltage at the terminal is set to a supply voltage of the common amplifier.
6. A circuit as claimed in claim 5 , wherein the voltage biasing means comprise a choke.
7. A circuit as claimed in claim 6 , wherein the choke is coupled between a voltage source and said terminal.
8. A circuit as claimed in claim 6 , wherein the choke is a printed waveguide.
9. A circuit as claimed in claim 1 , wherein, in the receive mode, the gain of the receive cascode is set in dependence on a common gate voltage applied to the gate of the common amplifier.
10. A circuit as claimed in claim 9 , wherein the common gate voltage is selected so as to match the input impedance of the circuit with the impedance of the antenna.
11. A circuit as claimed in claim 1 , wherein, in the transmit mode, a common gate voltage is applied to the gate of the common amplifier sufficient to hold the common amplifier at or close to its maximum gain.
12. A circuit as claimed in claim 11 , wherein the common gate voltage is a supply voltage of the common amplifier.
13. A circuit as claimed in claim 1 , wherein the common gate voltage is modified in dependence on a load condition at the antenna and/or the estimated transmission power from the antenna.
14. A circuit as claimed in claim 1 , wherein the receive amplifier is coupled to a tuneable resonant circuit such that, in the receive mode, the receive cascode preferentially amplifies radio frequency signals within a predetermined frequency of the resonant frequency of said resonant circuit.
15. A circuit as claimed in claim 1 , further comprising a switch connected between the input node and a supply voltage of the circuit, the switch being configured to:
in the receive mode, clamp the voltage at the input node to the supply voltage of the circuit so as to hold the transmit amplifier in its off state;
in the transmit mode, isolate the voltage at the input node from the supply voltage of the circuit.
16. A circuit as claimed in claim 1 , wherein the common, receive and transmit amplifiers are all n-type or all p-type field effect transistors and the supply voltages of the circuit are selected accordingly.
17. A circuit as claimed in claim 1 , wherein the circuit is an integrated circuit and the common amplifier is a double oxide MOSFET and the transmit and receive amplifiers are single oxide MOSFETs.
18. A circuit as claimed in claim 17 , wherein the common amplifier operates at a higher supply voltage than the transmit and receive amplifiers.
19. A circuit as claimed in claim 1 , wherein the receive cascode forms a low noise amplifier.
20. A circuit as claimed in claim 1 , wherein the transmit cascode forms a power amplifier.