Fine gain tuning
View Patent ↗A circuit tuneable between first and second frequencies comprising gain control circuitry operable to control the gain of the circuit between the first and second frequencies, the gain control circuitry comprising a resistor network having: at least two resistor lines arranged in parallel, each resistor line comprising one or more resistors; and for each resistor line, a switch operable to select or deselect the corresponding resistor line; the resistor lines and switches being arranged such that the net resistance of the resistor network is the parallel sum of each of the selected resistor lines; and logic circuitry configured to control said switches so as to minimize the variation in gain of the circuit between the first and second frequencies.
1. A circuit tuneable between first and second resonant frequencies comprising gain control circuitry operable to control a gain of the circuit between said first and second resonant frequencies, the gain control circuitry comprising:
a resistor network having:
at least two resistor lines arranged in parallel, each resistor line comprising one or more resistors; and
for each resistor line, a switch operable to select or deselect the resistor line;
the resistor lines and switches being arranged such that a net resistance of the resistor network is a parallel sum of each of the selected resistor lines; and
logic circuitry configured to control said switches so as to minimize a variation in gain of the circuit as the resonant frequency of the circuit changes between the first and second frequencies.
2. The circuit of claim 1 , wherein the circuit includes an inductance and a capacitance arranged together so as to form a resonant circuit tuneable between the first and second frequencies.
3. The circuit of claim 1 , wherein the resistor network is connected across the resonant circuit.
4. The circuit of claim 1 , wherein the circuit is a tuning circuit in a receive path of a radio receiver.
5. The circuit of claim 1 , wherein the circuit is an amplifier circuit in a transmit path of a radio transmitter.
6. The circuit of claim 1 , wherein each switch is responsive to digital levels of the logic circuitry.
7. The circuit of claim 1 , wherein the logic circuitry further comprises a memory operable to store a plurality of digital words, each digital word representing a state of the said switches.
8. The circuit of claim 7 , wherein the logic circuitry is operable to control the said switches in accordance with the stored digital words.
9. The circuit of claim 8 , wherein, during operation the logic circuitry is configured to select a digital work in dependence on a frequency to which the circuit is tuned and to control the said switches in accordance with that digital word.
10. The circuit of claim 8 , wherein, during operation, the logic circuitry is configured to select a digital word in dependence on a frequency band or sub-band to which the circuit is tuned and to control the said switches in accordance with that digital word.
11. The circuit of claim 7 , wherein the digital words are stored during manufacture.
12. The circuit of claim 7 , wherein the digital words are stored during a calibration process performed on the circuit.
13. The circuit of claim 7 , wherein the digital words are periodically updated during operation of the circuit.
14. The circuit of claim 13 , wherein the digital words are updated in accordance with a trial and error algorithm configured to optimize a gain flatness of the circuit between the first and second frequencies.
15. The circuit of claim 7 , wherein the digital words are updated during operation of the circuit in response to the performance of the circuit dropping below a predetermined level.
16. The circuit of claim 1 , wherein the resistor DAC has a width of at least 3 bits.
17. The circuit of claim 1 , wherein the variation in gain of the circuit is less than 1 dB per bit.
18. The circuit of claim 1 , wherein each switch is a MOS transistor.
19. The circuit of claim 1 , wherein the circuit is a balanced circuit and each resistor line includes at least two resistors in a balanced arrangement about the switch of that resistor line.
20. The circuit of claim 1 , wherein the resistance of each switch when closed is at least a factor of 10 lower than the total resistance of the corresponding resistor line.
21. The circuit of claim 1 , wherein the first and second frequencies delineate the range of frequencies over which the circuit is configured to operate.
22. The circuit of claim 21 , wherein the range of frequencies is at least 500 MHz.
23. The circuit of claim 21 , wherein the circuit is a tuning circuit for UWB radio receiver and the range of frequencies includes an entire UWB sub-band.
24. The circuit of claim 21 , wherein the range of frequencies is at least 1500 MHz.
25. The circuit of claim 21 , wherein the circuit is a turning circuit for a UWB radio receiver and the range of frequencies includes an entire UWB band group.
26. The circuit of claim 1 , wherein a gain flatness of the circuit is better than 4 dB between the first and second frequencies.
27. The circuit of claim 1 , wherein a gain settling time of the circuit is less than 1 ns.
28. The circuit of claim 1 , wherein the circuit is embodies in a single integrated circuit.
29. A radio receiver comprising the circuit of claim 1 , the circuit being a tuning circuit arranged to receive signals from an antenna of the radio receiver.
30. The radio receiver of claim 29 , wherein the radio receiver is a UWB radio receiver.