Method and device for generating scrambling code

1. A method for generating a scrambling code, comprising:

acquiring initial sequences X0, Y0;

extending the initial sequences X0, Y0 for (└N/M┘+1) times, and obtaining extended sequences X*, Y*, wherein, the N is a positive integer, 0<M≦22, and “└ ┘” denotes rounded down;

acquiring phase offset column vectors; and

generating the scrambling code according to the extended sequences X*, Y* and the phase offset column vectors;

wherein, the step of acquiring the initial sequences X0, Y0 comprises:

according to the current user number, reading median values of sequences X, Y of a user by using an association relation between the user number and the median values of the sequences X, Y;

judging whether the user in the current processing period produces the scrambling code for the first time, if yes, selecting the initial configured sequences X, Y as the initial sequences X0, Y0; and

if not, selecting the read median values of the sequences X, Y as the initial sequences X0, Y0.

2. The method according to claim 1 , wherein, the step of extending the initial sequences X0, Y0 for (└N/M┘+1) times, and obtaining the extended sequences X*, Y* comprises:

making └N/M┘+1 be j, 0<q≦j; and

extending the initial sequences X0, Y0 for j times, so that the 0 th bit to the (24+M×(q−1)) th bit of a sequence Xq after the q th time' extension is the same as the 0 th bit to the (24+M×(q−1)) th bit of a sequence X(q−1) after the (q−1) th time' extension, the (25+M×(q−1)+k) th bit of the sequence Xq is a result by adding model 2 of the (M×(q−1)+k) th bit and the (M×(q−1)+k+3) th bit of the sequence X(q−1); and a sequence Yq after the q th time' extension is the same as the 0 th bit to the (24+M×(q−1)) th bit of a sequence Y(q−1) after the (q−1) th time' extension, the (25+M×(q−1)+k) th bit of the sequence Yq is a result by adding model 2 of the (M×(q−1)+k) th bit, the (M×(q−1)+k+1) th bit, the (M×(q−1)+k+2) th bit and the (M×(q−1)+k+3) th bit of the sequence Y(q−1); wherein, 0≦k≦21.

3. The method according to claim 1 , wherein, after the step of extending the initial sequences X0, Y0 for (└N/M┘+1) times, and obtaining the extended sequences X*, Y*, the method further comprises:

storing the (N+1) th bit to the (N+25) th bit of the extended sequences X*, Y*.

4. The method according to claim 1 , wherein, the step of generating the scrambling code according to the extended sequences X*, Y* and the phase offset column vectors comprises:

obtaining N phase offset continuous C long,1,x,n according to a formula C long,1,x,n [i]=^(X*[i+24: i] & C long,1,x,n phase offset column vector);

obtaining N phase offset continuous C long,2,x,n according to a formula C long,2,x,n [i]=^(X*[i+24: i] & C long,2,x,n phase offset column vector);

obtaining N phase offset continuous C long,1,y,n according to a formula C long,1,y,n [i]=^(Y*[i+24: i] & C long,1,y,n phase offset column vector);

obtaining N phase offset continuous C long,2,y,n according to a formula C long,2,y,n [i]=^(Y*[i+24: i] & C long,2,y,n phase offset column vector); and

generating the scrambling code C long,n ; wherein, the real part of the scrambling code C long,n is: Re[C long,n [i]]=C long,1,x,n [i]^C long,1,y,n [i], and the imaginary part is: Im[C long,n [i]]=(−1) i ×C long,1,x,n [i]^C long,1,y,n [i]^C long,2,x,n [(2└i/2┘)]^C long,2,y,n [(2└i/2┘)], wherein, 0≦i<N.

5. The method according to claim 1 , wherein, the N is a positive integer that is greater than 0 and less than 2560.

6. The method according to claim 2 , wherein, the N is a positive integer that is greater than 0 and less than 2560.

7. The method according to claim 3 , wherein, the N is a positive integer that is greater than 0 and less than 2560.

8. The method according to claim 4 , wherein, the N is a positive integer that is greater than 0 and less than 2560.

9. An apparatus for generating a scrambling code, comprising:

a first acquiring module, which is configured to acquire initial sequences X0, Y0 in the following way: according to the current user number, read median values of sequences X, Y of a user by using an association relation between the user number and the median values of the sequences X, Y; and

judge whether the user in the current processing period produces the scrambling code for the first time, if yes, select the initially configured sequences X, Y as the initial sequences X0, Y0; and if not, select the read median values of the sequences X, Y as the initial sequences X0, Y0;

an extension module, which is configured to extend the initial sequences X0, Y0 acquired by the first acquiring module for (└N/M┘+1) times, and obtain extended sequences X*, Y*; wherein, the N is a positive integer, 0<M≦22, and “└ ┘” denotes rounded down;

a second acquiring module, which is configured to acquire phase offset column vectors; and

a generation module, which is configured to generate the scrambling code according to the sequences X*, Y* extended by the extension module and the phase offset column vectors acquired by the second acquiring module.

10. The apparatus according to claim 9 , wherein, in order to extend for the initial sequences X0, Y0 for (└N/M┘+1) times to obtain the extended sequences X*, Y*, the extension module is configured to:

make └N/M┘+1 be j, 0<q≦j; and

extend the initial sequences X0, Y0 for j times, so that the 0 th bit to the (24+M×(q−1)) th bit of a sequence Xq after the q th time' extension is the same as the 0 th bit to the (24+M×(q−1)) th bit of a sequence X(q−1) after the (q−1) th time' extension, the (25+M×(q−1)+k) th bit of the sequence Xq is a result by adding model 2 of the (M×(q−1)+k) th bit and the (M×(q−1)+k+3) th bit of the sequence X(q−1); and a sequence Yq after the q th time' extension is the same as the 0 th bit to the (24+M×(q−1)) th bit of a sequence Y(q−1) after the (q−1) th time' extension, the (25+M×(q−1)+k) th bit of the sequence Yq is a result by adding model 2 of the (M×(q−1)+k) th bit, the (M×(q−1)+k+1) th bit, the (M×(q−1)+k+2) th bit and the (M×(q−1)+k+3) th bit of the sequence Y(q−1); wherein, 0≦k≦21.

11. The apparatus according to claim 9 , further comprising: a storage module, which is configured to store the (N+1) th bit to the (N+25) th bit of the extended sequences X*, Y*.

12. The apparatus according to claim 9 , wherein, the generation module comprises:

a first generation module, which is configured to: obtain N phase offset continuous C long,1,x,n according to a formula C long,1,x,n [i]=^(X*[i+24: i] & C long,1,x,n phase offset column vector); obtain N phase offset continuous C long,2,x,n according to a formula C long,2,x,n [i]^(X[i+24: i] & C long,2,x,n phase offset column vector); obtain N phase offset continuous C long,1,y,n according to a formula C long,1,y,n [i]=A (Y*[i+24: i] & C long,1,y,n phase offset column vector); and obtain N phase offset continuous C long,2,y,n according to a formula C long,2,y,n [i]=^(Y*[i+24: i] & C long,2,y,n phase offset column vector); and

a second generation module, which is configured to: generate the scrambling code C long,n ; wherein, the real part of the scrambling code C long,n is: Re[C long,n [i]]=C long,1,x,n [i]^C long,1,y,n [i], and the imaginary part is: Im[C long,n [i]]=(−1) i ×C long,1,x,n [i]^C long,1,y,n [i]^C long,2,x,n [(2└i/2┘)]^C long,2,y,n [(2└i/2┘)], wherein, 0≦i<N.