Serial processing method, parallel processing method of bit rate matching and device thereof

1. A parallel processing method of bit rate matching, comprising:

receiving a system bit data stream, a check 1 data stream and a check 2 data stream, performing interleaving processing on N system bit data in the received system bit data stream, and caching the N system bit data in a storage used for storing the system bit data in parallel;

respectively constituting corresponding data with data in the check 1 data stream and data in the check 2 data stream; wherein the corresponding data refers to: a first data to a last but one data in the check 1 data stream respectively corresponding with a second data to a last data in the check 2 data stream; a last data in the check 1 data stream corresponding with a NULL padded in the check 2 data stream, and a first data in the check 2 data stream corresponding with a NULL padded in the check 1 data stream;

performing interleaving processing on the corresponding data and caching the corresponding data in a storage used for storing the check bit data in parallel with a parallelism degree of N, until all of the corresponding data are processed, wherein each corresponding data is regarded as one data for interleaving processing by a same interleaving address generation;

reading valid data from the storage used for storing the system bit data and the storage used for storing the check bit data, and implementing the rate matching.

2. The method according to claim 1 , wherein

the step of reading valid data from the storage used for storing the system bit data and the storage used for storing the check bit data comprises:

according to a set address and a length of output data, reading valid system bit data in parallel from the storage used for storing the system bit data, and reading valid check bit data in parallel from the storage used for storing the check bits data.

3. The method according to claim 2 , wherein

when the storage used for storing system bit data is a single port storage, a number of the storages used for storing the system bit data is equal to a set parallelism degree;

when the storage used for storing the system bit data is a real dual-port storage, a number of the storages used for storing the system bit data is equal to one half of the set parallelism degree.

4. The method according to claim 2 , wherein

when the storage used for storing check data is a single port storage, a number of the storages used for storing the check data is equal to a set parallelism degree;

when the storage used for storing check data is a real dual-port storage, a number of the storages used for storing the check bits data is equal to one half of the set parallelism degree.

5. A parallel process apparatus of bit rate matching, comprising a controlling module, N interleaving address calculating modules and a puncturing module, wherein N is equal to a preset parallelism degree; wherein

the controlling module is configured to: control the N interleaving address calculating modules to perform interleaving processing on N system bit data in a received system data stream, and cache the N system bit data on which the interleaving processing is performed in a storage used for storing system bit data in parallel; and is further configured to respectively constitute the corresponding data with data in the check 1 data stream and data in the check 2 data stream; wherein the corresponding data refers to: a first data to a last but one data in the check 1 data stream respectively corresponding with a second data to a last data in the check 2 data stream; a last data in the check 1 data stream corresponding with a NULL padded in the check 2 data stream, and a first data in the check 2 data stream corresponding with a NULL padded in the check 1 data stream; and moreover is configured to control the N interleaving address calculating modules to perform interleaving processing on the corresponding data, and cache the N corresponding data with a parallelism degree of N on a storage used for storing check data in parallel;

the interleaving address calculating module is configured to: perform interleaving processing on system bit data according to control of the controlling module, and perform interleaving processing on the corresponding data with a parallelism degree of N until all of the corresponding data is processed; wherein each corresponding data is regarded as one data for interleaving processing by a same interleaving address generation device to process interleaving;

the puncturing module is configured to: read valid data from the storage used for storing the system bit data and the storage used for storing the check data, and implement the rate matching.

6. The apparatus according to claim 5 , wherein

the puncturing module is also configured to: read valid system bit data in parallel from the storage used for storing the system bit data, and read valid check data in parallel from the storage used for storing the check data.

7. The apparatus according to claim 6 , wherein

when the storage used for storing the system bit data is a single port storage, a number of the storages used for storing the system bit data is equal to a set parallelism degree;

when the storage used for storing the system bit data a dual-port storage, a number of the storages used for storing the system bit data is equal to one half of the set parallelism degree.

8. The apparatus according to claim 6 , wherein,

when the storage used for storing the check data is a single port storage, a number of the storages used for storing the check data is equal to a set parallelism degree;

when the storage used for storing the check data is a dual-port storage, a number of the storages used for storing the check data is equal to one half of a set parallelism degree.