IR detector system and method
View Patent ↗A system and method of reducing undesirable image artifacts such as image tear and image smearing are described. The system can include a series of pixels and enhanced sensitivity circuits. The circuit can be configured so as to operate in an enhanced sensitivity mode having a combination of sample and hold circuits and binning functions, the combination acting so as to reduce the undesirable imaging artifacts.
1. An infrared detector system, comprising:
a series of pixels in a staring array having associated circuits, wherein the staring array is divided into a series of pixel groups, each pixel group having an integration capacitance; and
enhanced sensitivity circuit means configured so as to operate in an enhanced sensitivity mode, wherein when image signal data is acquired, a hold capacitance of a first pixel group is electrically connected to a combined integration capacitance of the first pixel group and an adjacent second pixel group, and during integration periods, the hold capacitance of each of pixel group is configured to store a pixel signal voltage of the associated pixel group based on an integration of image signal data stored in the combined integration capacitance.
2. An IR detector system according to claim 1 , comprising:
a means configured to allow operation in standard sensitivity or enhanced binning modes to suit operational or imaging conditions.
3. An IR detector system according to claim 1 , in which the imaging artefacts include, but not be limited to, at least image tear and image smearing.
4. An IR detector system according to claim 1 , in which the system comprises:
means for increasing an amount of binning to decrease a likelihood of imaging artefacts and increase sensitivity.
5. An IR detector system according to claim 1 , wherein the enhanced sensitivity circuit means is configured for establishing a length of separation between image capture periods of the staring array equal to a reset period of the staring array.
6. An IR detector system according to claim 5 , wherein the reset period of the staring array is a reset period for an image capture field of the staring array.
7. An IR detector system according to claim 6 , wherein the image capture field is one of a plurality of image capture fields.
8. An infrared detector system according to claim 1 , wherein the enhanced sensitivity circuit includes a combination of an independently operable sample and hold circuit, a hold capacitor reset circuit, binning function means, and operational sequence means, said combination being configured for reducing undesirable imaging artifacts.
9. An infrared detector system according to claim 8 , in which the sample and hold circuit comprises:
control function means implemented and operated separately in each pixel group to provide enhanced binning.
10. An IR detector system according to claim 8 , in which the binning function means is configured for operation independently with the sample and hold circuit of each pixel group.
11. An IR detector system according to claim 8 , in which the system comprises:
means to maximise integration capacitance in each pixel group.
12. An IR detector system according to claim 8 , wherein the circuit means is configured for providing separate field readout requirements in a single readout frame.
13. An IR detector system according to claim 12 , comprising:
means to minimise time between the integration time of each pixel group.
14. An IR detector system according to claim 8 wherein the circuit means is configured to allow the pixel circuits to operate in non enhanced sensitivity mode.