IP Library Granted Patent US 9,245,765
Granted Patent B2
US 9,245,765 · App. 13/394,812 · Granted Jan 26, 2016

Apparatus and method of applying a film to a semiconductor wafer and method of processing a semiconductor wafer

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Quick Facts
Patent No.
US 9,245,765
App. No.
13/394,812
Granted
Jan 26, 2016
Kind
B2
Abstract

Implementations and techniques for applying a film to a semiconductor wafer and for processing a semiconductor wafer are generally disclosed.

Claims (14)

1. A semiconductor wafer that includes a plurality of vias, the semiconductor wafer comprising:

a supporting peripheral rim that protrudes from a first side of the semiconductor wafer;

a first dry film resist arranged on the first side of the semiconductor wafer within the supporting peripheral rim, wherein the first dry film resist is photo-structured to form a first opening on the first dry film resist so that a via of the plurality of vias remains revealed from the first dry film resist through the first opening, and wherein a diameter of the first opening is smaller than a diameter of the via revealed from the first dry film resist; and

a removable second dry film resist arranged on the first dry film resist, wherein the removable second dry film resist is photo-structured to form a second opening on the removable second dry film resist and a diameter of the second opening is larger than the diameter of the via revealed from the first dry film resist.

2. The semiconductor wafer according to claim 1 , wherein the first dry film resist has cut edges.

3. The semiconductor wafer according to claim 1 , wherein at least a portion of the first dry film resist forms an integral part of a semiconductor chip.

4. The semiconductor wafer according to claim 1 , further comprising a bump positioned on the first dry film resist, the bump being positioned over a bump landing area that is offset from the via.

5. The semiconductor wafer according to claim 1 , further comprising a bump positioned on the first dry film resist and positioned over the via.

6. The semiconductor wafer according to claim 1 , wherein the supporting peripheral rim comprises a plurality of perforations.

7. The semiconductor wafer according to claim 6 , wherein the plurality of perforations extend from an inner side wall to an outer side wall of the supporting peripheral rim.

8. The semiconductor wafer according to claim 1 , wherein the first dry film resist includes a plurality of openings corresponding to the plurality of vias and each diameter of the plurality of openings is smaller than each diameter of the plurality of vias.

9. The semiconductor wafer according to claim 1 , wherein the first dry film resist is a permanent resist.

10. The semiconductor wafer according to claim 1 , further comprising a bump deposited in the second opening.

11. The semiconductor wafer according to claim 1 , wherein first dry film resist and the removable second dry film resist comprise different materials.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED ON JANUARY 29, 2019 AT REEL 048373 FRAME 0217 Recorded Sep 22, 2025
From: CRESTLINE DIRECT FINANCE, L.P., AS COLLATERAL AGENT
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 072936/0464 →
SECURITY INTEREST Recorded Jan 29, 2019
From: EMPIRE TECHNOLOGY DEVELOPMENT LLC
To: CRESTLINE DIRECT FINANCE, L.P.
Reel/Frame 048373/0217 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2012
From: BIECK, FLORIAN
To: DOUBLECHECK SEMICONDUCTORS PTE. LTD.
Reel/Frame 027832/0400 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2012
From: DOUBLECHECK SEMICONDUCTORS PTE. LTD.
To: SCHWEIGER, MARTIN
Reel/Frame 027832/0406 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2012
From: SCHWEIGER, MARTIN
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 027832/0412 →