Integrated circuit, computer system, and control method, including power saving control to reduce power consumed by execution of a loop

1. An integrated circuit provided with a processor, comprising:

a loop detection unit configured to detect execution of a loop in the processor, each iteration of the loop including one or more instructions;

a loop-carried dependence analysis unit configured to analyze the loop in order to detect loop-carried dependence between instructions in two different iterations of the loop;

a power control unit configured to perform power saving control to reduce power consumed by execution of the loop when the loop-carried dependence analysis unit detects no loop-carried dependence in the loop; and

a loop termination detection unit configured to detect termination of execution of the loop, wherein

while performing the power saving control, the power control unit terminates the power saving control when the loop termination detection unit detects the termination of execution of the loop.

2. The integrated circuit of claim 1 , wherein

the loop-carried dependence analysis unit detects the loop-carried dependence in the loop by detecting that a value written into a variable in a first iteration is read from the variable in a second iteration executed after the first iteration.

3. The integrated circuit of claim 2 , wherein

the loop detection unit detects that the processor is executing a loop by detecting that the processor executes a branch instruction that branches to a previous address.

4. The integrated circuit of claim 3 , further comprising:

a loop range storage unit for storing a range of the loop, wherein

upon detecting the branch instruction that branches to a previous address, the loop detection unit outputs the range of the loop to the loop range storage unit and instructs the loop-carried dependence analysis unit to analyze for loop-carried dependence, and

the loop-carried dependence analysis unit analyzes an instruction sequence in the range of the loop stored in the loop range storage unit.

5. The integrated circuit of claim 4 , wherein

the loop termination detection unit detects the termination of execution of a loop by detecting that a branch instruction has been executed to branch outside of the range of the loop stored in the loop range storage unit, or by detecting that when a conditional branch instruction located at an end of the range of the loop is executed, a branch is not taken.

6. The integrated circuit of claim 4 , wherein

the loop range storage unit stores information including a starting address and an ending address of the loop.

7. The integrated circuit of claim 4 , wherein

the processor is provided with an instruction sequence storage unit for storing a fetched instruction sequence, and

the loop-carried dependence analysis unit analyzes the instruction sequence in the range of the loop stored in the instruction sequence storage unit.

8. The integrated circuit of claim 7 , wherein

the instruction sequence stored in the instruction sequence storage unit includes a pre-fetched instruction.

9. The integrated circuit of claim 1 , wherein

the power control unit performs the power saving control by decreasing a frequency of a clock provided to the processor and terminates the power saving control by increasing the frequency of the clock provided to the processor.

10. The integrated circuit of claim 1 , wherein

the power control unit performs the power saving control by decreasing voltage of power provided to the processor and terminates the power saving control by increasing the voltage of power provided to the processor.

11. The integrated circuit of claim 1 , wherein

the power control unit

performs the power saving control by decreasing both voltage of power provided to the processor and a frequency of a clock provided to the processor and

terminates the power saving control by increasing both the voltage of power provided to the processor and the frequency of the clock provided to the processor.

12. The integrated circuit of claim 1 , wherein

the processor is provided with a plurality of execution units, and

the power control unit performs the power saving control by stopping execution of a portion of the plurality of execution units and terminates the power saving control by restarting execution of the portion of the plurality of execution units whose execution was stopped.

13. The integrated circuit of claim 1 , wherein

the processor is provided with a thread management unit configured to manage time slices allocated in one-to-one correspondence to a plurality of threads, and

the power control unit

performs the power saving control by instructing the thread management unit to decrease the time slice allocated to a thread in a busy-wait, the thread in the busy-wait executing a loop in which no loop-carried dependence is detected, and

terminates the power saving control by instructing the thread management unit to increase the time slice allocated to the thread in the busy-wait.

14. The integrated circuit of claim 13 , wherein

the power control unit

performs the power saving control by instructing the thread management unit to decrease the time slice allocated to the thread in the busy-wait and by decreasing a frequency of a clock provided to the processor, and

terminates the power saving control by instructing the thread management unit to increase the time slice allocated to the thread in the busy-wait and by increasing the frequency of the clock provided to the processor.

15. The integrated circuit of claim 14 , wherein

the power control unit performs the power saving control by decreasing the frequency of the clock provided to the processor in proportion to a decrease in the time slice allocated to the thread in the busy-wait.

16. The integrated circuit of claim 13 , wherein

the processor is provided with a plurality of execution units, and

the power control unit

performs the power saving control by instructing the thread management unit to decrease the time slice allocated to the thread in the busy-wait and by stopping execution of a portion of the plurality of execution units, and

terminates the power saving control by instructing the thread management unit to increase the time slice allocated to the thread in the busy-wait and by restarting execution of the portion of the plurality of execution units.

17. The integrated circuit of claim 16 , wherein

the power control unit performs the power saving control by decreasing a number of execution units in operation among the plurality of execution units in proportion to a decrease in the time slice allocated to the thread in the busy-wait.

18. The integrated circuit of claim 13 , wherein

the processor is provided with a plurality of execution units, and

the power control unit

performs the power saving control by instructing the thread management unit to decrease the time slice allocated to the thread in the busy-wait, by decreasing a frequency of a clock provided to the processor, and by stopping execution of a portion of the plurality of execution units, and

terminates the power saving control by instructing the thread management unit to increase the time slice allocated to the thread in the busy-wait, by increasing the frequency of the clock provided to the processor, and by restarting execution of the portion of the plurality of execution units.

19. The integrated circuit of claim 13 , wherein

the power control unit

performs the power saving control by instructing the thread management unit to decrease the time slice allocated to the thread in the busy-wait, by decreasing a frequency of a clock provided to the processor, and by decreasing voltage of power provided to the processor, and

terminates the power saving control by instructing the thread management unit to increase the time slice allocated to the thread in the busy-wait, by increasing the frequency of the clock provided to the processor, and by increasing the voltage of power provided to the processor.

20. An integrated circuit provided with a processor, comprising:

a loop detection unit configured to detect execution of a loop in the processor, each iteration of the loop including one or more instructions;

a loop-carried dependence analysis unit configured to analyze the loop in order to detect loop-carried dependence between instructions in two different iterations of the loop; and

a power control unit configured to perform power saving control to reduce power consumed by execution of the loop when the loop-carried dependence analysis unit detects no loop-carried dependence in the loop, wherein

the loop-carried dependence analysis unit detects the loop-carried dependence when an instruction in the loop reads from and writes to a same variable.

21. A control method for a computer system provided with a processor, comprising the steps of:

detecting execution of a loop in the processor, each iteration of the loop including one or more instructions;

analyzing the loop in order to detect loop-carried dependence between instructions in two different iterations of the loop;

performing power saving control to reduce power consumed by execution of the loop when no loop-carried dependence is detected in the loop; and

detecting termination of execution of the loop, wherein

while performing the power saving control, the power saving control is terminated when the termination of execution of the loop is detected.

22. A computer system provided with a processor, comprising:

a loop detection unit configured to detect execution of a loop in the processor, each iteration of the loop including one or more instructions;

a loop-carried dependence analysis unit configured to analyze the loop in order to detect loop-carried dependence between instructions in two different iterations of the loop;

a power control unit configured to perform power saving control to reduce power consumed by execution of the loop when the loop-carried dependence analysis unit detects no loop-carried dependence in the loop; and

a loop termination detection unit configured to detect termination of execution of the loop, wherein,

while performing the power saving control, the power control unit terminates the power saving control when the loop termination detection unit detects the termination of execution of the loop.