Pipeline method and system for switching packets
View Patent ↗A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.
1. A network device comprising:
a media access controller (MAC) configured to receive a packet received by the network device;
a first series of elements configured to forward from the media access controller (MAC) to a backplane, the first series of elements comprising a first processor and a first memory, the first processor configured to process the packet and store corresponding packet data in the first memory;
a second series of elements configured to forward data from the backplane to the MAC, the second series of elements comprising a second processor and a second memory; and
a path that enables the packet data to be forwarded from an element in the first series of elements to an element in the second series of elements without using the backplane, wherein the element in the first series of elements is a first application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) and the element in the second series of elements is a second FPGA, wherein the first ASIC or FPGA is different from the second FPGA;
wherein the element in the second series of elements, which receives the packet data forwarded using the path, is configured to:
store the packet data in the second memory; and
notify the second processor after the packet data has been stored in the second memory.
2. The network device of claim 1 wherein the path enables the packet data to be forwarded from the first memory to the element in the second series of elements.
3. The network device of claim 1 wherein the element in the second series of elements is further configured to receive, from the backplane, packet data corresponding to a second packet received by the network device.
4. The network device of claim 1 further comprising:
a chassis comprising a set of slots; and
a blade inserted into a slot from the set of slots, wherein the blade comprises the MAC, the first series of elements, and the second series of elements.
5. The network device of claim 1 wherein at least one element from the first series of elements is a field programmable gate array (FPGA).
6. The network device of claim 1 wherein at least one element from the first series of elements is an application-specific integrated circuit (ASIC).
7. The network device of claim 1 wherein the element in the first series of elements from which the packet data is forwarded is configured to read the packet data from the first memory and determine a destination for the packet data.
8. A method comprising:
receiving, at a media access controller (MAC) in a network device, a packet received by the network device;
providing, in the network device, a first series of elements configured to forward data from the media access controller (MAC) to a backplane of the network device, the first series of elements comprising a first processor and a first memory;
providing, in the network device, a second series of elements configured to forward data from the backplane to the MAC, the second series of elements comprising a second processor and a second memory;
processing the packet, by the first processor, and storing corresponding packet data in the first memory;
forwarding, from an element in the first series of elements to an element in the second series of elements, the packet data without using the backplane, wherein the element in the first series of elements is a first application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) and the element in the second series of elements is a second FPGA, wherein the first ASIC or FPGA is different from the second FPGA;
storing, by the element in the second series of elements that receives the packet data, the packet data in the second memory; and
notifying, by the element in the second series of elements, the second processor after the packet data has been stored in the second memory.
9. The method of claim 8 wherein the forwarding comprises forwarding the packet data from the first memory to the element in the second series of elements.
10. The method of claim 8 further comprising receiving, by the element in the second series of elements, from the backplane, data corresponding to a second packet received by the network device.
11. The method of claim 8 further comprising:
providing a chassis in the network device, the chassis comprising a set of slots; and
providing a blade inserted into a slot from the set of slots, wherein the blade comprises the MAC, the first series of elements, and the second series of elements.
12. The method of claim 8 further comprising:
reading, by the element in the first series of elements from which the packet data is forwarded, the packet data from the first memory; and
determining, by the element in the first series of elements from which the packet data is forwarded, a destination for the packet data.
13. The network device of claim 1 wherein the first processor is configured to receive the packet from the MAC.
14. The network device of claim 1 further comprising a content addressable memory (CAM) associated with the first processor, and wherein the first processor is configured to cause a lookup to be performed for the packet using the CAM.
15. The network device of claim 1 wherein the first memory is a dual-port memory and the second memory is a dual-port memory.
16. The method of claim 8 further comprising receiving, by the first processor, the packet from the MAC.
17. The method of claim 8 further comprising:
causing, by the first processor, a lookup to be performed for the packet using a content addressable memory (CAM) associated with the first processor.
18. The method of claim 8 wherein the first memory is a dual-port memory and the second memory is a dual-port memory.