IP Library › Granted Patent US 8,918,612
Granted Patent B1
US 8,918,612 · App. 13/400,256 · Granted Dec 23, 2014

Method and apparatus for verifying memory contents

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Quick Facts
Patent No.
US 8,918,612
App. No.
13/400,256
Granted
Dec 23, 2014
Kind
B1
Abstract

A system and method of verifying a content of a non-volatile reprogrammable memory communicatively coupled to a microprocessor is disclosed. The method comprises the steps of reading at least a portion of the data stored in the non-volatile reprogrammable memory via a second communication path secured by encryption, generating a computed integrity value according to at least a portion of the contents of the non-volatile reprogrammable memory, and reading an integrity value, and comparing the computed integrity value with the read integrity value.

Claims (48)

1. An apparatus, comprising:

a microprocessor;

a non-volatile reprogrammable memory communicatively coupled to the microprocessor via a first communication path, the non-volatile reprogrammable memory for storing data including microprocessor program instructions; and

a logical module, communicatively coupled to the non-volatile reprogrammable memory via a second communication path independent from the first communication path, the logical module for securely reading at least a portion of the data stored in the non-volatile reprogrammable memory, for reading a stored integrity value from a source independent from the non-volatile reprogrammable memory and the second communication path, and for verifying the at least a portion of the data stored in the non-volatile reprogrammable memory according to the read at least a portion of the data stored in the non-volatile reprogrammable memory and the read integrity value;

wherein the stored integrity value is read from an internal memory of the microprocessor.

2. The apparatus of claim 1 , wherein the logical module verifies all of the data stored in the non-volatile reprogrammable memory.

3. The apparatus of claim 1 , wherein the logical module verifies only a portion of the data stored in the non-volatile reprogrammable memory.

4. The apparatus of claim 1 , wherein:

the logical module generates a computed integrity value from the at least a portion of the data stored in the non-volatile reprogrammable memory and the at least a portion of the data stored in the non-volatile programmable memory is verified by comparing the computed integrity value with the read integrity value.

5. The apparatus of claim 1 , wherein the logical module further reports a result of the comparison to the microprocessor.

6. The apparatus of claim 5 , wherein:

the microprocessor is communicatively coupled to the logical module via a third communication path independent of the first communication path and the second communication path; and

wherein the result of the comparison is reported via the third communication path.

7. The apparatus of claim 1 , wherein the logical module removes power from the microprocessor according to the result of the comparison.

8. A method of verifying a content of a non-volatile reprogrammable memory communicatively coupled to a microprocessor via a first communication path, the non-volatile memory for storing data including microprocessor program instructions, the method comprising the steps of:

reading, in a logic module independent from the microprocessor, at least a portion of the data stored in the non-volatile reprogrammable memory via a second communication path independent from the first communication path;

generating, in the logic module, a computed integrity value according to the read at least a portion of the data;

reading an integrity value from a source independent from the non-volatile reprogrammable memory and the second communication path; and

comparing the computed integrity value with the read integrity value;

wherein the source independent from the non-volatile reprogrammable memory is an internal memory of the microprocessor.

9. The method of claim 8 , further comprising the step of transmitting a success signal if the computed integrity value favorably compares with the read integrity value and a failure signal if the computed integrity value does not favorably compare with the read integrity value.

10. The method of claim 9 , wherein the success signal is transmitted to the microprocessor via a third communication path independent from the first communication path and the second communication path.

11. The method of claim 8 , further comprising the step of removing power from the microprocessor according to the comparison of the computed integrity value and the read integrity value.

12. An apparatus, comprising:

a microprocessor;

a non-volatile reprogrammable memory communicatively coupled to the microprocessor via a first communication path, the non-volatile reprogrammable memory for storing data including microprocessor program instructions; and

a logical module, communicatively coupled to the non-volatile reprogrammable memory via a second communication path independent from the first communication path, the logical module for securely reading at least a portion of the data stored in the non-volatile reprogrammable memory, for reading a stored integrity value from a source independent from the non-volatile reprogrammable memory and the second communication path, and for verifying the at least a portion of the data stored in the non-volatile reprogrammable memory according to the read at least a portion of the data stored in the non-volatile reprogrammable memory and the read integrity value;

wherein the microprocessor is communicatively coupled to the logical module via a third communication path independent of the first communication path and the second communication path; and

wherein the logical module further reports a result of the comparison to the microprocessor via the third communication path.

13. The apparatus of claim 12 , wherein the logical module verifies all of the data stored in the non-volatile reprogrammable memory.

14. The apparatus of claim 12 , wherein the logical module verifies only a portion of the data stored in the non-volatile reprogrammable memory.

15. The apparatus of claim 12 , wherein:

the logical module generates a computed integrity value from the at least a portion of the data stored in the non-volatile reprogrammable memory and the at least a portion of the data stored in the non-volatile programmable memory is verified by comparing the computed integrity value with the read integrity value.

16. The apparatus of claim 12 , wherein the stored integrity value is read from a memory communicatively coupled to the logical module.

17. The apparatus of claim 12 , wherein the stored integrity value is read from an internal memory of the microprocessor.

18. The apparatus of claim 12 , wherein the stored integrity value is read from the logical module.

19. The apparatus of claim 12 , wherein the logical module removes power from the microprocessor according to the result of the comparison.

20. A method of verifying a content of a non-volatile reprogrammable memory communicatively coupled to a microprocessor via a first communication path, the non-volatile memory for storing data including microprocessor program instructions, the method comprising the steps of:

reading, in a logic module independent from the microprocessor, at least a portion of the data stored in the non-volatile reprogrammable memory via a second communication path independent from the first communication path;

generating, in the logic module, a computed integrity value according to the read at least a portion of the data;

reading an integrity value from a source independent from the non-volatile reprogrammable memory and the second communication path;

comparing the computed integrity value with the read integrity value; and

transmitting a success signal if the computed integrity value favorably compares with the read integrity value and a failure signal if the computed integrity value does not favorably compare with the read integrity value, wherein the success signal is transmitted to the microprocessor via a third communication path independent from the first communication path and the second communication path.

21. The method of claim 20 , wherein the source independent from the non-volatile reprogrammable memory is an internal memory of the microprocessor.

22. The method of claim 20 , wherein the source independent from the non-volatile reprogrammable memory is the logical module.

23. The method of claim 20 , further comprising the step of:

verifying the read integrity value by a comparison with a signature of the integrity value.

24. The method of claim 20 , further comprising the step of removing power from the microprocessor according to the comparison of the computed integrity value and the read integrity value.