Power device manufacture on the recessed side of a thinned wafer
View Patent ↗A recess is formed into a first side of a wafer such that a thinned center portion of the wafer is formed, and such that the central portion is surrounded by a thicker peripheral edge support portion. The second side of the wafer remains substantially entirely planar. After formation of the thinned wafer, vertical power devices are formed into the first side of the central portion of the wafer. Formation of the devices involves forming a plurality of diffusion regions into the first side of the thinned central portion. Metal electrodes are formed on the first and second sides, the peripheral portion is cut from the wafer, and the thin central portion is diced to form separate power devices. In one example, a first commercial entity manufactures the thinned wafers, and a second commercial entity obtains the thinned wafers and performs subsequent processing to form the vertical power devices.
1. A method comprising:
(a) obtaining a thinned disc-shaped semiconductor wafer, wherein a recess extends into a first side of the wafer such that the wafer has a thinner central portion and a thicker peripheral edge support portion;
(b) forming a P-type isolation zone in the thinner central portion of the first side of the wafer;
(c) forming a P-type diffusion region in a second side of the wafer opposite the first side such that the P-type isolation zone overlaps the P-type diffusion region, wherein the thicker peripheral edge support portion is a part of the wafer at the time of the forming of (b) and the forming of (c);
(d) forming a glassivation layer over the P-type isolation zone; and
(e) further processing the wafer after (b), (c) and (d) and thereby forming a plurality of semiconductor devices, wherein the P-type isolation zone formed in (b), the P-type diffusion region formed in (c), and the glassivation layer formed in (d) are parts of one of the semiconductor devices.
2. The method of claim 1 , wherein the one of the semiconductor devices is a vertical power device taken from the group consisting of: a power diode, and a power bipolar transistor.
3. The method of claim 1 , wherein the first side of the thinner central portion has a planar surface, wherein the planar surface has a disc-shape with a substantially circular circumference, and wherein the planar surface is more than three inches wide.
4. The method of claim 1 , wherein the second side of the wafer opposite the first side extends substantially entirely in a plane.
5. The method of claim 1 , wherein the obtaining of the wafer in (a) is accomplished by an action taken from the group consisting of: a) purchasing the thinned wafer, and b) manufacturing the thinned wafer.
6. The method of claim 1 , wherein the glassivation layer is formed over the first side of the thinner central portion of the wafer, wherein the thicker peripheral edge support portion is a part of the wafer at the time of the forming of the glassivation layer, and wherein the glassivation layer is at least ten microns thick.
7. The method of claim 1 , wherein (e) involves removing the thicker peripheral edge support portion and dicing the thinner central portion.
8. The method of claim 1 , wherein the thicker peripheral edge support portion has a plurality of radially extending slits.
9. A method comprising:
(a) obtaining a thinned disc-shaped semiconductor wafer, wherein a recess extends into a first side of the wafer such that the wafer has a thinner central portion and a thicker peripheral edge support portion, wherein a second side of the wafer opposite the first side extends substantially entirely in a plane;
(b) forming a first doped region into the first side of the thinner central portion of the wafer;
(c) forming a second doped region in the second side of the wafer such that the first doped region overlaps the second doped region;
(d) forming a glassivation layer over the first doped region, wherein the thicker peripheral edge support portion is a part of the wafer at the time of the forming of (b), the forming of (c) and the forming of (d); and
(e) dicing the wafer to form a plurality of semiconductor devices, wherein the first doped region formed in (b), the second doped region formed in (c), and the glassivation layer formed in (d) are parts of one of the semiconductor devices.
10. The method of claim 9 , wherein one of the semiconductor devices is a vertical power device, and wherein the vertical power device is taken from the group consisting of: a power diode, a power field effect transistor, a power insulated gate bipolar transistor.
11. The method of claim 9 , wherein the first doped region is a P-type isolation zone.
12. The method of claim 11 , wherein the second doped region is a P-type diffusion region.
13. The method of claim 9 , wherein the thinner central portion of the wafer is not greater than two hundred microns thick.
14. The method of claim 9 , wherein the thinner central portion of the wafer has a planar surface, wherein the planar surface has a disc-shape with a substantially circular circumference, and wherein the planar surface is more than three inches wide.
15. The method of claim 9 , wherein the thicker peripheral edge support portion has a cylindrical sidewall.
16. The method of claim 9 , wherein the first doped region formed in (b) is an isolation structure.
17. The method of claim 9 , further comprising before (e):
(f) forming a cathode diffusion region into the thinner central portion.
18. The method of claim 17 , further comprising before (e):
(g) forming a cathode metal electrode over the cathode diffusion region.
19. The method of claim 18 , further comprising before (e):
(h) forming an anode metal electrode on the second side of the wafer.
20. The method of claim 9 , wherein a cathode of a diode is formed into the first side of the thinner central portion of the wafer.
21. The method of claim 9 , wherein a gate of a transistor is formed into the first side of the thinner central portion of the wafer.
22. The method of claim 9 , wherein an emitter of a transistor is formed into the first side of the thinner central portion of the wafer.
23. The method of claim 9 ,
wherein the glassivation layer is more than ten microns thick.