Apparatus and method for phase locked loop bandwidth expansion
View Patent ↗An apparatus for PLL bandwidth expansion including a compensation filter and a phase locked loop, where the compensation filter is programmed with a compensation function derived based on programmable coefficients and parameters of a transmitting device, a frequency response of the phase locked loop, and a wanted frequency response.
1. An apparatus for phase locked loop (“PLL”) bandwidth expansion comprising:
a transmitting device including a compensation filter and a PLL installed in front of the compensation filter, the compensation filter configured to be programmed with a compensation function having filter coefficients,
wherein the filter coefficients are set from programmable coefficients and parameters of a transmitting device, and
wherein a function of the compensation filter (“Fcomp(s)”) is:
F
comp
(
s
)
=
d
0
*
(
s
3
+
s
2
*
c
2
+
s
*
c
1
+
c
0
)
c
1
*
(
s
3
+
s
2
*
a
2
+
s
*
a
1
+
a
0
)
where
d
0
=
w
a
2
c
0
=
a
*
K
ϕ
*
A
*
b
*
K
vco
N
c
1
=
K
ϕ
*
A
*
b
*
K
vco
N
c 2 =b
a 0 =a *wa 2
a 1 =wa 2 *√ 2 *a *wa
a 2 =√ 2 *wa +a
and where s is a Laplace transform operator (jw), d 0 , C 0 , c 1 , c 2 , a 0 , a 1 , and a 2 are the filter coefficients, and K φ , K VCO , A, N, a, b, w, wa, and ξ are the programmable coefficients and parameters such that K φ includes phase detector gain, K VCO includes voltage controlled oscillator gain, A includes a gain value, N includes a variable divider value, a includes a ‘zero’, b includes a ‘pole’, w includes a filter natural frequency, wa is a desired bandwidth, and includes a damping factor, and
wherein a frequency response of the PLL combined with the compensation filter (“Freq(s)”)is:
Freq
(
s
)
=
w
a
2
s
2
+
2
ξ
*
wa
*
s
+
wa
2
.
2. The apparatus of claim 1 , wherein the derivation of the compensation function is also based on a frequency response of the PLL and a wanted frequency response.
3. The apparatus of claim 1 , wherein the compensation filter is programmed with the compensation function by programming the filter coefficients of a digital state variable 3 rd order or higher compensator.
4. The apparatus of claim 1 , wherein the compensation filter is one of: an application specific integrated circuit, a field programmable gate array, and a combination of an application specific integrated circuit and a field programmable gate array.
5. The apparatus of claim 1 , wherein the transmitting device is a VSAT.
6. The apparatus of claim 1 , wherein the compensation filter is programmed with the compensation function by programming the filter coefficients of a filter comprising a filter topology.
7. The apparatus of claim 1 , wherein the programmable coefficients and parameters include a zero of the PLL, a pole of the PLL, a voltage-controlled oscillator gain, a phase detector gain, a variable divider value, and a damping factor.
8. An apparatus for phase locked loop (“PLL”) bandwidth expansion comprising:
a compensation filter; and
a PLL installed in front of the compensation filter,
wherein the compensation filter is programmed with a compensation function having filter coefficients that are set from programmable coefficients and parameters of a transmitting device, a frequency response of the PLL, and a wanted frequency response, and
wherein the compensation function (“Fcomp(s)”) is:
F
comp
(
s
)
=
d
0
*
(
s
3
+
s
2
*
c
2
+
s
*
c
1
+
c
0
)
c
1
*
(
s
3
+
s
2
*
a
2
+
s
*
a
1
+
a
0
)
where
d
0
=
w
a
2
c
0
=
a
*
K
ϕ
*
A
*
b
*
K
vco
N
c
1
=
K
ϕ
*
A
*
b
*
K
vco
N
c 2 =b
a 0 =a *wa 2
a 1 =wa 2 *√ 2 *a *wa
a 2 =√ 2 *wa +a
and where s is a Laplace transform operator (jw), d 0 , C 0 , c 1 , c 2 , a 0 , a 1 , and a 2 are the filter coefficients, and K φ , K VCO , A, N, a, b, w, wa, and ξ are the programmable coefficients and parameters such that K φ includes phase detector gain, K VCO , includes voltage controlled oscillator gain, A includes a gain value, N includes a variable divider value, a includes a ‘zero’, b includes a ‘pole’, w includes a filter natural frequency, wa is a desired bandwidth, and includes a damping factor, and
wherein a frequency response of the PLL combined with the compensation filter (“Freq(s)”)is:
Freq
(
s
)
=
w
a
2
s
2
+
2
ξ
*
wa
*
s
+
wa
2
.
9. The apparatus of claim 8 , wherein the compensation function is a function for the wanted frequency response divided by a function for the frequency response of the PLL.
10. The apparatus of claim 8 , wherein the compensation function includes one of: a 5 th order function, a 4 th order function, and a 3 rd order function.
11. The apparatus of claim 8 , wherein the compensation filter and the PLL in combination produce a Butterworth response.
12. The apparatus of claim 8 , wherein the transmitting device is a VSAT, and wherein the programmable coefficients and parameters are stored in an outdoor unit of the VSAT.
13. The apparatus of claim 8 , wherein the compensation filter is programmed with the compensation function by programming the filter coefficients of digital state variable 3 rd order or higher compensator.
14. A method for phase locked loop (“PLL”) bandwidth expansion comprising:
determining, via a processor, programmable coefficients and parameters;
deriving, via the processor, a compensation function including filtering coefficients based on the programmable coefficients and parameters;
determining, via the processor, a function for a frequency response of a PLL installed in front of a compensation filter that includes the compensation function; and
implementing, via the processor, the compensation function of the compensation filter within the transmitting device,
wherein the compensation function (“Fcomp(s)”) is:
F
comp
(
s
)
=
d
0
*
(
s
3
+
s
2
*
c
2
+
s
*
c
1
+
c
0
)
c
1
*
(
s
3
+
s
2
*
a
2
+
s
*
a
1
+
a
0
)
where
d
0
=
w
a
2
c
0
=
a
*
K
ϕ
*
A
*
b
*
K
vco
N
c
1
=
K
ϕ
*
A
*
b
*
K
vco
N
c 2 =b
a 0 =a *wa 2
a 1 =wa 2 *√ 2 *a *wa
a 2 =√ 2 *wa +a
and where s is a Laplace transform operator (jw), d 0 , C 0 , c 1 , c 2 , a 0 , a 1 , and a 2 are the filter coefficients, and K φ , K VCO , A, N, a, b, w, wa, and ξ are the programmable coefficients and parameters such that K φ includes phase detector gain, K VCO , includes voltage controlled oscillator gain, A includes a gain value, N includes a variable divider value, a includes a ‘zero’, b includes a ‘pole’, w includes a filter natural frequency, wa is a desired bandwidth, and includes a damping factor, and
wherein a frequency response of the PLL combined with the compensation filter (“Freq(s)”) is:
Freq
(
s
)
=
w
a
2
s
2
+
2
ξ
*
wa
*
s
+
wa
2
.
15. The method of claim 14 , further comprising reading the programmable coefficients and parameters stored on the transmitting device.
16. The method of claim 14 , wherein deriving the compensation function based on the programmable coefficients and parameters further comprises:
determining, via the processor, a function for a wanted frequency response; and
dividing, via the processor, the function for the wanted frequency response by the function for the frequency response of the PLL.
17. The method of claim 14 , wherein the compensation function includes one of: a 5 th order function, a 4 th order function, and a 3 rd order function.
18. The method of claim 14 , wherein implementing the compensation function further comprises programming the filter coefficients of a digital state variable 3 rd order or higher compensator.
19. The method of claim 18 , wherein the digital state variable 3 rd order compensator is implemented in a field programmable gate array.
20. The method of claim 18 , wherein the digital state variable 3 rd order compensator is implemented in an application specific integrated circuit.