Method for manufacturing a semiconductor structure
View Patent ↗A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other.
1. A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, comprising the step of manufacturing of a PNP-type structure by:
forming a p-emitter layer having an overlying surface oxide layer on top of an NPN-type structure including a NPN-emitter, the p-emitter layer comprising lateral and vertical surfaces; and
removing the surface oxide layer using an ion etching step, wherein the ion etching step uses a plasma for providing ions wherein the plasma is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other.
2. The method according to claim 1 , wherein a process pressure and the acceleration voltage are defined so as to set an anisotropy of the ion etching process to a value that is lower than 50%.
3. The method according to claim 1 , wherein for generation of the plasma, an RF-power of more than 350 W is applied.
4. The method according to claim 1 , wherein a processing time for the ion etching step is lower than 90 s.
5. The method according to claim 1 , wherein no wafer cooling is applied during the ion etching step.
6. The method according to claim 1 , wherein for generation of the plasma, an RF-power of 600 W is applied.
7. The method according to claim 1 , wherein a processing time for the ion etching step is lower than 60 s.
8. The method according to claim 1 , wherein an etching gas that is free from CHF 3 is applied.
9. The method according to claim 1 , wherein a wafer temperature of more than 40° C. is applied.
10. The method according to claim 1 , wherein for the ion etching step, a process pressure is set to a value for which a mean free path of the accelerated ions is lower than a distance between the plasma and the wafer.
11. The method of claim 10 , wherein the process pressure is set to a value between 10 and 30 mTorr.
12. The method of claim 10 , wherein the process pressure is set to a value of 20 mTorr.
13. The method according to claim 1 , wherein the acceleration voltage is set to a value that is insufficient for sputtering of the oxide layer.
14. The method according to claim 13 , wherein the acceleration voltage is set to zero.
15. The method according to claim 1 , wherein an etching gas causing no polymerization thereof is applied.
16. The method according to claim 15 , wherein O 2 is added to the etching gas, and C 2 F 6 is applied as the etching gas.