System and method for ensuring partitioned block physical compatibility between revisions of an integrated circuit design
View Patent ↗Differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit can be determined by comparing an image of pins of a partitioned logic block in a first floorplan of the integrated circuit with an image of pins of the partitioned logic block in a second floorplan of the integrated circuit. The second floorplan can represent a new floorplan design resulting from a change to an integrated circuit design represented by the first floorplan. If no differences exist between pins of the partitioned logic block in the first and second floorplans, information representing the partitioned logic block in the second floorplan can be substituted with information representing the partitioned logic block in the first floorplan.
1. A method for determining differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit, comprising:
providing a programmed processor system with one or more data files including first information representing an image of pins of the partitioned logic block in a first floorplan of an integrated circuit;
providing a programmed processor system with one or more data files including second information representing an image of pins of the partitioned logic block in a second floorplan of the integrated circuit;
the programmed processor system comparing the first information with the second information to determine differences between locations of the pins of the partitioned logic block in the first floorplan and the locations of the pins of the partitioned logic block in the second floorplan; and
the programmed processor system processing one or more data files to substitute information representing the partitioned logic block in the second floorplan with information representing the partitioned logic block in the first floorplan if it is determined that no differences exist between locations of the pins of the partitioned logic block in the first floorplan and the locations of the pins of the partitioned logic block in the second floorplan.
2. The method of claim 1 , wherein providing the programmed processor system with the first information comprises:
identifying in a first input data file data representing pins of the partitioned logic block in the first floorplan of the integrated circuit; and
forming a first modified data file having only the data from the first input data file representing pins of the partitioned logic block in the first floorplan of the integrated circuit.
3. The method of claim 2 , further comprising converting the first modified data file to an image file format, wherein the programmed processor system comparing the first information with the second information comprises the programmed processor system comparing the first modified data file with another data file.
4. The method of claim 3 , wherein providing the programmed processor system with the second information comprises:
identifying in a second input data file data representing pins of the partitioned logic block in the second floorplan of the integrated circuit; and
forming a second modified data file having only the data from the second input data file representing pins of the partitioned logic block in the second floorplan of the integrated circuit.
5. The method of claim 4 , further comprising converting the second modified data file to an image file format, wherein the programmed processor system comparing the first information with the second information comprises the programmed processor system comparing the first modified data file with the second modified data file.
6. The method of claim 5 , wherein the programmed processor system comparing the first modified data file with the second modified data file comprises the programmed processor system performing an exclusive-OR operation between the first modified data file and the second modified data file.
7. A system for determining differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit, comprising:
a user interface;
a memory subsystem storing first information representing an image of pins of the partitioned logic block in a first floorplan of an integrated circuit and second information representing an image of pins of the partitioned logic block in a second floorplan of the integrated circuit;
a processor system, the processor system programmed to:
compare the first information with the second information to determine differences between locations of the pins of the partitioned logic block in the first floorplan and the locations of the pins of the partitioned logic block in the second floorplan; and
process one or more data files to substitute information representing the partitioned logic block in the second floorplan with information representing the partitioned logic block in the first floorplan if it is determined that no differences exist between locations of the pins of the partitioned logic block in the first floorplan and the locations of the pins of the partitioned logic block in the second floorplan.
8. The system of claim 7 , wherein the processor system is further programmed to:
identify in a first input data file data representing pins of the partitioned logic block in the first floorplan of the integrated circuit; and
form a first modified data file having only the data from the first input data file representing pins of the partitioned logic block in the first floorplan of the integrated circuit.
9. The system of claim 8 , wherein the processor system is further programmed to convert the first modified data file to an image file format, wherein the programmed processor system compares the first information with the second information by comparing the first modified data file with another data file.
10. The system of claim 9 , wherein the processor system is further programmed to:
identify in a second input data file data representing pins of the partitioned logic block in the second floorplan of the integrated circuit; and
form a second modified data file having only the data from the second input data file representing pins of the partitioned logic block in the second floorplan of the integrated circuit.
11. The system of claim 10 , the processor system is further programmed to convert the second modified data file to an image file format, wherein the programmed processor system compares the first information with the second information by comparing the first modified data file with the second modified data file.
12. The system of claim 11 , wherein the processor system is programmed to compare the first modified data file with the second modified data file by performing an exclusive-OR operation between the first modified data file and the second modified data file.
13. A computer program product for determining differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit, the computer program product comprising a non-transitory computer-usable medium on which is stored in computer-executable form instructions for causing a computer system to effect a method comprising:
providing first information representing an image of pins of the partitioned logic block in a first floorplan of an integrated circuit;
providing second information representing an image of pins of the partitioned logic block in a second floorplan of the integrated circuit;
comparing the first information with the second information to determine differences between locations of the pins of the partitioned logic block in the first floorplan and the locations of the pins of the partitioned logic block in the second floorplan; and
substituting information representing the partitioned logic block in the second floorplan with information representing the partitioned logic block in the first floorplan if it is determined that no differences exist between locations of the pins of the partitioned logic block in the first floorplan and the locations of the pins of the partitioned logic block in the second floorplan.
14. The computer program product of claim 13 , wherein providing the first information comprises:
identifying in a first input data file data representing pins of the partitioned logic block in the first floorplan of the integrated circuit; and
forming a first modified data file having only the data from the first input data file representing pins of the partitioned logic block in the first floorplan of the integrated circuit.
15. The computer program product of claim 14 , further comprising instructions for causing the computer system to convert the first modified data file to an image file format, wherein comparing the first information with the second information by comparing the first modified data file with another data file.
16. The computer program product of claim 15 , wherein providing the second information comprises:
identifying in a second input data file data representing pins of the partitioned logic block in the second floorplan of the integrated circuit; and
forming a second modified data file having only the data from the second input data file representing pins of the partitioned logic block in the second floorplan of the integrated circuit.
17. The computer program product of claim 16 , further comprising further comprising instructions for causing the computer system to convert the second modified data file to an image file format, wherein comparing the first information with the second information comprises comparing the first modified data file with the second modified data file.
18. The computer program product of claim 17 , wherein comparing the first modified data file with the second modified data file comprises performing an exclusive-OR operation between the first modified data file and the second modified data file.