IP Library › Granted Patent US 8,520,463
Granted Patent B2
US 8,520,463 · App. 13/403,014 · Granted Aug 27, 2013

Semiconductor integrated circuit

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Quick Facts
Patent No.
US 8,520,463
App. No.
13/403,014
Granted
Aug 27, 2013
Kind
B2
Abstract

A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor.

Claims (55)

1. A semiconductor integrated circuit comprising a memory macro including:

a plurality of memory cells arranged in a matrix;

a plurality of word lines corresponding to rows of the plurality of memory cells; and

a plurality of word line drivers configured to drive the plurality of word lines,

wherein a voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor,

the voltage of the word lines is set at a first voltage if the threshold voltage of the n-channel transistor is lower than a predetermined voltage, at a second voltage if the threshold voltage of the n-channel transistor is higher than the predetermined voltage, and at the first or second voltage if the threshold voltage of the n-channel transistor is equal to the predetermined voltage, and

the predetermined voltage increases with increase in the absolute value of the threshold voltage of the p-channel transistor linearly or in a curve.

2. The semiconductor integrated circuit of claim 1 , wherein the first voltage is lower than the second voltage.

3. The semiconductor integrated circuit of claim 1 , wherein the p-channel transistor and the n-channel transistor are transistors constituting a semiconductor integrated circuit.

4. The semiconductor integrated circuit of claim 1 , wherein the p-channel transistor and the n-channel transistor are transistors constituting a memory macro.

5. The semiconductor integrated circuit of claim 1 , wherein the p-channel transistor and the n-channel transistor are transistors constituting a memory cell.

6. The semiconductor integrated circuit of claim 1 , wherein the p-channel transistor and the n-channel transistor are transistors for measuring a memory cell characteristic.

7. The semiconductor integrated circuit of claim 6 , wherein the transistors for measuring a memory cell characteristic are provided for each semiconductor integrated circuit.

8. The semiconductor integrated circuit of claim 6 , wherein the transistors for measuring a memory cell characteristic are provided on a scribe lane of a wafer.

9. The semiconductor integrated circuit of claim 1 , wherein the voltage of the word lines in their activated state varies among chips.

10. The semiconductor integrated circuit of claim 1 , wherein the voltage of the word lines in their activated state varies among memory macros.

11. A semiconductor integrated circuit comprising a memory macro including:

a plurality of memory cells arranged in a matrix;

a plurality of word lines corresponding to rows of the plurality of memory cells; and

a plurality of word line drivers configured to drive the plurality of word lines,

wherein a voltage of the word lines in their activated state is set to vary with saturation current characteristics of a p-channel transistor and an n-channel transistor,

the voltage of the word lines is set at a first voltage if the saturation current of the re-channel transistor is lower than a predetermined current value, at a second voltage if the saturation current of the n-channel transistor is higher than the predetermined current value, and at the first or second voltage if the saturation current of the n-channel transistor is equal to the predetermined current value, and

the predetermined current value increases with increase in the absolute value of the saturation current value of the p-channel transistor linearly or in a curve.

12. The semiconductor integrated circuit of claim 11 , wherein the first voltage is higher than the second voltage.

13. The semiconductor integrated circuit of claim 11 , wherein the p-channel transistor and the n-channel transistor are transistors constituting a semiconductor integrated circuit.

14. The semiconductor integrated circuit of claim 11 , wherein the p-channel transistor and the n-channel transistor are transistors constituting a memory macro.

15. The semiconductor integrated circuit of claim 11 , wherein the p-channel transistor and the n-channel transistor are transistors constituting a memory cell.

16. The semiconductor integrated circuit of claim 11 , wherein the p-channel transistor and the n-channel transistor are transistors for measuring a memory cell characteristic.

17. The semiconductor integrated circuit of claim 16 , wherein the transistors for measuring a memory cell characteristic are provided for each semiconductor integrated circuit.

18. The semiconductor integrated circuit of claim 16 , wherein the transistors for measuring a memory cell characteristic are provided on a scribe lane of a wafer.

19. The semiconductor integrated circuit of claim 11 , wherein the voltage of the word lines in their activated state varies among chips.

20. The semiconductor integrated circuit of claim 11 , wherein the voltage of the word lines in their activated state varies among memory macros.

21. A semiconductor integrated circuit comprising a memory macro including:

a plurality of memory cells arranged in a matrix;

a plurality of word lines corresponding to rows of the plurality of memory cells; and

a plurality of word line drivers configured to drive the plurality of word lines,

wherein a voltage of the word lines in their activated state is set to vary with drain-source leak current characteristics of a p-channel transistor and an n-channel transistor,

the voltage of the word lines is set at a first voltage if the drain-source leak current of the n-channel transistor is lower than a predetermined current value, at a second voltage if the drain-source leak current of the n-channel transistor is higher than the predetermined current value, and at the first or second voltage if the drain-source leak current of the n-channel transistor is equal to the predetermined current value, and

the predetermined current value increases with increase in the absolute value of the drain-source leak current of the p-channel transistor linearly or in a curve.

22. The semiconductor integrated circuit of claim 21 , wherein the first voltage is higher than the second voltage.

23. The semiconductor integrated circuit of claim 21 , wherein the p-channel transistor and the n-channel transistor are transistors constituting a semiconductor integrated circuit.

24. The semiconductor integrated circuit of claim 21 , wherein the p-channel transistor and the n-channel transistor are transistors constituting a memory macro.

25. The semiconductor integrated circuit of claim 21 , wherein the p-channel transistor and the n-channel transistor are transistors constituting a memory cell.

26. The semiconductor integrated circuit of claim 21 , wherein the p-channel transistor and the n-channel transistor are transistors for measuring a memory cell characteristic.

27. The semiconductor integrated circuit of claim 26 , wherein the transistors for measuring a memory cell characteristic are provided for each semiconductor integrated circuit.

28. The semiconductor integrated circuit of claim 26 , wherein the transistors for measuring a memory cell characteristic are provided on a scribe lane of a wafer.

29. The semiconductor integrated circuit of claim 21 , wherein the voltage of the word lines in their activated state varies among chips.

30. The semiconductor integrated circuit of claim 21 , wherein the voltage of the word lines in their activated state varies among memory macros.

31. A semiconductor integrated circuit comprising a memory macro including:

a plurality of memory cells arranged in a matrix;

a plurality of word lines corresponding to rows of the plurality of memory cells; and

a plurality of word line drivers configured to drive the plurality of word lines,

wherein a voltage of the word lines in their activated state is set to change at a given chip temperature, and

the voltage of the word lines is set at a seventh voltage if the chip temperature is lower than the given chip temperature and at an eighth voltage if the chip temperature is higher than the given chip temperature.

32. The semiconductor integrated circuit of claim 31 , wherein the seventh voltage is higher than the eighth voltage.