IP Library Granted Patent US 8,923,362
Granted Patent B2
US 8,923,362 · App. 13/403,201 · Granted Dec 30, 2014

Wireless communications system with secondary synchronization code based on values in primary synchronization code

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Quick Facts
Patent No.
US 8,923,362
App. No.
13/403,201
Granted
Dec 30, 2014
Kind
B2
Abstract

A wireless communication system. The system comprises transmitter circuitry (BST 1 ), the transmitter circuitry comprising encoder circuitry ( 50 ) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry ( 501 ) for providing the primary synchronization code in response to a first sequence ( 32 ). The encoder circuitry further comprises circuitry ( 502 ) for providing the secondary synchronization code in response to a second sequence ( 54 ) and a third sequence ( 56 ). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

Claims (42)

1. A method of forming synchronization codes for a wireless communication device, comprising:

A. providing a primary synchronization code in response to a first sequence; and

B. providing a secondary synchronization code in response to a second sequence and a third sequence of logical one and minus-one values, the third sequence being different from the first sequence;

i. the second sequence is selected from a plurality of sequences, each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences;

ii. the second sequence includes a plurality of code words and each of the plurality of code words is selected from a plurality of Hadamard sequences;

iii. the second sequence consists of sixteen of the code words; and

iv. the third sequence includes a sequence of hits from the first sequence, the sequence of bits from the first sequence is repeated a plurality of times in the third sequence; and

C. outputting the primary synchronization code and the secondary synchronization code from synchronization code generator circuitry.

2. The method of claim 1 , wherein the first sequence includes a hierarchical sequence,

3. The method of claim 1 , in which the first sequence includes a Golay sequence.

4. A method of forming synchronization codes for a wireless communication device, comprising:

A. providing a primary synchronization code in response to a first sequence; and

B. providing a secondary synchronization code in response to a second sequence and a third sequence of logical one and minus-one values, the third sequence being different from the first sequence;

i. the second sequence is selected from a plurality of sequences, each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences;

ii. the second sequence includes a plurality of code words and each of the plurality of code words is selected from a plurality of Hadamard sequences;

iii. the second sequence includes sixteen of the code words; and

iv. the third sequence includes a sequence of bits from the first sequence, the sequence of bits from the first sequence is repeated a plurality of times in the third sequence; and

C. outputting the primary synchronization code and the secondary synchronization code from synchronization code generator circuitry.

5. The method of claim 4 , wherein the first sequence includes a hierarchical sequence.

6. The method of claim 4 , in which the first sequence includes a Golay sequence.

7. A method of forming synchronization codes for a wireless communication device, comprising;

A. providing a primary synchronization code in response to a first sequence; and

B. providing a secondary synchronization code in response to a second sequence and a third sequence of logical one and minus-one values, the third sequence being different from the first sequence;

i. the second sequence is selected from a plurality of sequences, each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences;

ii. the second sequence includes a plurality of code words and each of the plurality of code words is selected from a plurality of Hadamard sequences;

iii. the second sequence includes at least sixteen of the code words; and

iv. the third sequence includes a sequence of bits from the first sequence, the sequence of bits from the first sequence is repeated a plurality of times in the third sequence; and

C. outputting the primary synchronization code and the secondary synchronization code from synchronization code generator circuitry.

8. The method of claim 7 , wherein the first sequence includes a hierarchical sequence.

9. The method of claim 7 , in which the first sequence includes a Golay sequence.

10. The method of claim 1 , wherein the logical one and minus-one values comprise a group of values {1, 1, 1, 1, 1, 1, −1, −1}.

11. The method of claim 1 , wherein the logical one and minus-one values comprise a group of values {1, −1, 1, −1, 1, −1, −1}.

12. The method of claim 1 , wherein the logical one and minus-one values comprise a first group of values {1, 1, 1, 1, 1, 1, −1, −1} and a second group of values {1, −1, 1, −1, 1, −1, −1, 1}.

13. The method of claim 12 , wherein the first and second group of values are real values that translate to binary bit numbers by converting a −1 real value to a binary value of 1 and by converting a 1 real value to a binary value of 0.

14. The method of claim 4 , wherein the logical one and minus-one values comprise a group of values {1, 1, 1, 1, 1, 1, −1, −1 }.

15. The method of claim 4 , wherein the logical one and minus-one values comprise a group of values {1, −1, 1, −1, 1, −1, −1, 1 }.

16. The method of claim 4 , wherein the logical one and minus-one values comprise a first group of values {1, 1, 1, 1, 1, 1, −1, −1} and a second group of values {1, −1, 1, −1, 1, −1, −1, 1}.

17. The method of claim 16 , wherein the first and second group of values are real values that translate to binary bit numbers by converting a −1 real value to a binary value of 1 and by converting a 1 real value to a binary value of 0.

18. The method of claim 7 , wherein the logical one and minus-one values comprise a group of values {1, 1, 1, 1, 1, 1, −1, −1}.

19. The method of claim 7 , wherein the logical one and minus-one values comprise a group of values {1, −1, 1, −1, 1, −1, −1, 1}.

20. The method of claim 7 , wherein the logical one and minus-one values comprise a first group of values {1, 1, 1, 1, 1, 1, −1, −1} and a second group of values {1, −1, 1, −1, 1, −1, −1, 1}.

21. The method of claim 20 , wherein the first and second group of values are real values that translate to binary hit numbers by converting a −1 real value to a binary value of 1 and by converting a 1 real value to a binary value of 0.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 052414/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2017
From: TEXAS INSTRUMENTS INCORPORATED
To: INTEL CORPORATION
Reel/Frame 041383/0040 →