Wireless communications system with secondary synchronization code based on values in primary synchronization code
View Patent ↗A wireless communication system. The system comprises transmitter circuitry (BST 1 ), the transmitter circuitry comprising encoder circuitry ( 50 ) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry ( 501 ) for providing the primary synchronization code in response to a first sequence ( 32 ). The encoder circuitry further comprises circuitry ( 502 ) for providing the secondary synchronization code in response to a second sequence ( 54 ) and a third sequence ( 56 ). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.
1. A method of forming synchronization codes for a wireless communication device,
comprising the steps of:
providing in an apparatus the primary synchronization code in response to a first sequence; and
providing the secondary synchronization code in response to a second sequence and a third sequence of logical one and minus-one values, the third sequence being different from the first sequence; and
wherein the second sequence is selected from a plurality of sequences, wherein each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences; and
wherein the third sequence comprises a sequence of bits from the first sequence, wherein the sequence of bits from the first sequence is repeated a plurality of times in the third sequence.
2. The method of claim 1 , wherein the first sequence comprises a hierarchical sequence.
3. The method of claim 1 , wherein the first sequence comprises a Golay sequence.
4. The method of claim 1 , wherein the second sequence comprises a plurality of code words, and wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.
5. The method of claim 4 , wherein the second sequence consists of fifteen of the code words.
6. The method of claim 5 , wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences.
7. The method of claim 6 , wherein the 256 Walsh sequences have a defined order; and wherein the plurality of Hadamard sequences comprise sixteen Hadamard sequences selected as every sixteenth sequence in the defined order.
8. The method of claim 4 , wherein the second sequence consists of sixteen of the code Word.
9. The method of claim 8 , wherein the 256 Walsh sequences have a defined order, and wherein the plurality of Hadamard sequences comprise seventeen Hadamard sequences selected as every eighth sequence in the defined order.
10. The method of claim 1 , wherein the step of providing the secondary synchronization code comprises:
performing an exclusive OR operation between the second sequence and the third sequence; and
providing the secondary synchronization code in response to the exclusive OR operation.
11. The method of claim 1 , wherein the primary synchronization code consists of 8-bit
values A and B and complements of the values A and B;
wherein the value A comprises a sequence A={1, 1, 1, 1, 1, 1, −1, −1};
wherein the value B comprises a sequence B=1, −1, 1, −1, 1, −1, −1, 1 1;
wherein a value C is defined as a sequence C={A, −B};
wherein the third sequence comprises a 256-bit sequence {C, C, C, −C, C, C, −C, −C, C, −C, C, −C, −C, −C, −C, −C}.
12. The method of claim 11 , wherein the step of providing the secondary synchronization code comprises:
performing an exclusive OR operation between the second sequence and the third sequence; and
providing the secondary synchronization code in response to the exclusive OR operation.
13. The method of claim 2 , wherein the second sequence comprises a plurality of code words, and wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.
14. The method of claim 13 , wherein the plurality of Hadamard sequences are selected
from a set of 256 Walsh sequences, wherein the 256 Walsh sequences have a defined order, and wherein the plurality of Hadamard sequences comprise sixteen Hadamard sequences selected as every sixteenth sequence in the defined order.
15. The method of claim 1 , wherein the step of providing the secondary synchronization code comprises providing the secondary synchronization code from a storage circuit.
16. A method of encoding a synchronization code, comprising the steps of:
producing in an apparatus a primary synchronization code comprising a first code sequence;
producing a secondary synchronization code comprising a second code sequence combined with a third code sequence of logical one and minus-one values, the third code sequence being different from the first code sequence;
wherein the second code sequence is from a plurality of sequences;
wherein each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences; and
wherein the third code sequence comprises a sequence of bits of the fast code sequence, and wherein the sequence of bits of the first code sequence is repeated a plurality of times in the third sequence.
17. The method of claim 16 , wherein the second code sequence comprises 256 bits, and wherein the third code sequence comprises 32 repeated instances of the a subset of bits from the first code sequence.
18. The method of claim 17 , wherein the step of producing the secondary synchronization code comprises performing an exclusive OR operation of the second code sequence with the third code sequence.
19. The method of claim 18 , wherein the second code sequence comprises a plurality of code words, and wherein each code word of the plurality of code words is selected from a plurality of Hadamard sequences.
20. The method of claim 16 , wherein each of the second and third code sequences comprise 256 bits, and wherein the subset of bits from the first code sequence comprises a fourth code sequence of bits and a complement of the fourth code sequence of bits.
21. The method of claim 20 , wherein the step of producing the secondary synchronization code comprises performing an exclusive OR operation of the second code sequence with the third code sequence.
22. The method of claim 21 , wherein the second code sequence comprises a plurality of code words, and wherein each code word of the plurality of code words is selected from a plurality of Hadamard sequences.
23. The method of claim 22 , wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences, wherein the 256 Walsh sequences have a defined order, and wherein the plurality of Hadamard sequences comprise seventeen Hadamard sequences selected as every eighth sequence in the defined order.
24. The method of claim 1 , wherein the logical one and minus-one values comprise a group of values {1, 1, 1, 1, 1, −1, −1}.
25. The method of claim 1 , wherein the logical one and minus-one values comprise a group of values {1, −1, 1, −1, 1, −1, −1, 1}.
26. The method of claim 1 , wherein the logical one and minus-one values comprise a first group of values {1, 1, 1, 1, 1, 1, −1, −1} and a second group of values {1, −1, 1, −1, 1, −, −1, 1}.
27. The method of claim 26 , wherein the first and second group of values are real values that translate to binary bit numbers by converting a −1 real value to a binary value of 1 and by converting a 1 real value to a binary value of 0.
28. The method of claim 16 , wherein the logical one and minus-one values comprise a group of values {1, 1, 1, 1, 1, 1, −1, −1}.
29. The method of claim 16 , wherein the logical one and minus-one values comprise a group of values {1, −1, 1, −1, 1, −1, −1, 1}.
30. The method of claim 16 , wherein the logical one and minus-one values comprise a first group of values {1, 1, 1, 1, 1, 1, −1, −1} and a second group of values {1, −1, 1, −1, 1, −1, −, 1}.
31. The method of claim 30 , wherein the first and second group of values are real values that translate to binary bit numbers by converting a −1 real value to a binary value of 1 and by converting a 1 real value to a binary value of 0.