IP Library Granted Patent US 8,681,834
Granted Patent B2
US 8,681,834 · App. 13/403,236 · Granted Mar 25, 2014

Wireless communications system with secondary synchronization code based on values in primary synchronization code

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Quick Facts
Patent No.
US 8,681,834
App. No.
13/403,236
Granted
Mar 25, 2014
Kind
B2
Abstract

A wireless communication system. The system comprises transmitter circuitry (BST 1 ), the transmitter circuitry comprising encoder circuitry ( 50 ) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry ( 501 ) for providing the primary synchronization code in response to a first sequence ( 32 ). The encoder circuitry further comprises circuitry ( 502 ) for providing the secondary synchronization code in response to a second sequence ( 54 ) and a third sequence ( 56 ). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

Claims (12)

1. A method of decoding a synchronization code, comprising the steps of:

identifying in an apparatus a primary synchronization code comprising a first code sequence;

identifying in the apparatus a secondary synchronization code comprising a second code sequence combined with a third code sequence, the third code sequence being different from the first code sequence,

wherein the second code sequence is from a plurality of sequences;

wherein each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences; and

wherein the third code sequence comprises a sequence of bits of the first code sequence, and wherein the sequence of bits of the first code sequence is repeated a plurality of times in the third sequence.

2. The method of claim 1 , wherein the second code sequence comprises 256 bits, and

wherein the third code sequence comprises 32 repeated instances of the a subset of bits from the first code sequence.

3. The method of claim 2 , wherein the second code sequence comprises a plurality of code words, and wherein each code word of the plurality of code words is selected from a plurality of Hadamard sequences.

4. The method of claim 1 , wherein each of the second and third code sequences comprise 256 bits, and wherein the subset of bits from the first code sequence comprises a fourth code sequence of bits and a complement of the fourth code sequence of bits.

5. The method of claim 4 , wherein the second code sequence comprises a plurality of code words, and wherein each code word of the plurality of code words is selected from a plurality of Hadamard sequences.

6. The method of claim 5 , wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences, wherein the 256 Walsh sequences have a defined order, and wherein the plurality of Hadamard sequences comprise seventeen Hadamard sequences selected as every eighth sequence in the defined order.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 052414/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2017
From: TEXAS INSTRUMENTS INCORPORATED
To: INTEL CORPORATION
Reel/Frame 041383/0040 →