DDR PSRAM and data writing and reading methods thereof
A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory.
1. A double data rate pseudo SRAM (DDR PSRAM), comprising:
a data receiver, receiving a first single data rate data from a controller via a common bus according to a clock, and receiving a double data rate data from the controller via the common bus according to a data strobe signal from the controller;
a memory; and
an address decoder, decoding the first single data rate data to obtain an address of the memory,
wherein the data receiver stores the double data rate data into the address of the memory.
2. The DDR PSRAM as claimed in claim 1 , wherein the data receiver receives the first single data rate data in a command phase and the double data rate data in a write data phase.
3. The DDR PSRAM as claimed in claim 1 , wherein the clock and the data strobe signal are provided by the controller, and the data strobe signal is two times the frequency of the clock.
4. The DDR PSRAM as claimed in claim 3 , wherein the double data rate data comprises a plurality of data units that are divided into a first group and a second group, and the data receiver receives the data units of the first group in response to a rising edge of the data strobe signal and receives the data units of the second group in response to a falling edge of the data strobe signal.
5. The DDR PSRAM as claimed in claim 1 , wherein the data receiver comprises:
a single data rate unit, receiving the first single data rate data in a command phase and providing the first single data rate data to the address decoder; and
a double data rate unit, receiving the double data rate data in a write data phase and storing the double data rate data into the memory.
6. The DDR PSRAM as claimed in claim 1 , wherein the data receiver receives a second single data rate from the controller or the double data rate data via the common bus in a write data phase according to a control signal.
7. The DDR PSRAM as claimed in claim 6 , wherein the data receiver comprises:
a single data rate unit, receiving the second single data rate data in the write data phase and storing the second single data rate data into the address of the memory when the control signal indicates that the DDR PSRAM is operated in a single data rate mode; and
a double data rate unit, receiving the double data rate data in the write data phase and storing the double data rate data into the address of the memory when the control signal indicates that the DDR PSRAM is operated in a double data rate mode.
8. The DDR PSRAM as claimed in claim 7 , wherein the control signal is determined according to a command from the controller or a hardware configuration of the DDR PSRAM.
9. A data writing method for a double data rate pseudo SRAM (DDR PSRAM), comprising:
obtaining a first single data rate data from a controller via a common bus according to a clock;
decoding the first single data rate data to obtain an address of a memory within the DDR PSRAM;
obtaining a double data rate data from the controller via the common bus according to a data strobe signal from the controller; and
storing the double data rate data into the address of the memory.
10. The data writing method as claimed in claim 9 , wherein the first single data rate data is received in a command phase and the double data rate data is received in a write data phase.
11. The data writing method as claimed in claim 9 , wherein the double data rate data comprises a plurality of data units that are divided into a first group and a second group, and the step of obtaining the double data rate data via the common bus according to the data strobe signal from the controller further comprises:
obtaining the data units of the first group in response to a rising edge of the data strobe signal; and
obtaining the data units of the second group in response to a falling edge of the data strobe signal.
12. The data writing method as claimed in claim 9 , further comprises:
obtaining a second single data rate data from the controller via the common bus in a write data phase when a control signal indicates that the DDR PSRAM is operated in a single data rate mode; and
storing the second single data rate data into the address of the memory,
wherein the double data rate data is received in the write data phase when the control signal indicates that the DDR PSRAM is operated in a double data rate mode.