Manufacturing process of thin film transistor
View Patent ↗A thin film transistor includes a gate, a gate insulator layer, a channel layer, a source, a drain, and an ohmic contact layer. The gate insulator layer covers the gate; the channel layer is disposed on the gate insulator layer above the gate; the source and the drain are disposed on the channel layer; the ohmic contact layer is disposed between the channel layer and the source and drain. The ohmic contact layer is constituted by a number of film layers. As mentioned above, the thin film transistor has an ohmic contact layer constituted by a number of film layers. When the thin film transistor is turned off, the current leakage thereof is lowered than that of a conventional thin film transistor.
1. A manufacturing process of a thin film transistor, comprising:
forming a gate on a substrate;
forming a gate insulator layer on the substrate to cover the gate;
forming a channel layer on the gate insulator layer over the gate;
forming an ohmic contact layer on the channel layer, wherein the ohmic contact layer is constituted by a plurality of N-doped amorphous silicon layers; and
forming a source and a drain on the ohmic contact layer, wherein the ohmic contact layer is located between the source and the drain is removed.
2. The manufacturing process of the thin film transistor of claim 1 , wherein a method of forming the ohmic contact layer comprises:
utilizing a deposition process, wherein a deposition power is changed during the deposition process so as to form the N-doped amorphous silicon layers to constitute the ohmic contact layer having the N-doped amorphous silicon layers.
3. The manufacturing process of the thin film transistor of claim 2 , wherein a way to change the deposition power during the deposition process comprises turning off the power at a predetermined time interval during the deposition process.
4. The manufacturing process of the thin film transistor of claim 1 , wherein a method of forming the ohmic contact layer comprises:
utilizing a deposition process, wherein a deposition pressure condition is changed during the deposition process so as to form the N-doped amorphous silicon layers to constitute the ohmic contact layer having the N-doped amorphous silicon layers.
5. The manufacturing process of the thin film transistor of claim 4 , wherein a way to change the deposition pressure condition during the deposition process comprises changing the pressure at a predetermined time interval during the deposition process, so as to lower the deposition rate.
6. A manufacturing process of a thin film transistor, comprising:
forming a gate on a substrate;
forming a gate insulator layer on the substrate to cover the gate;
forming a channel layer on the gate insulator layer over the gate;
forming an ohmic contact layer on the channel layer, wherein the ohmic contact layer is constituted by a plurality of N-doped amorphous silicon layers; and
forming a source and a drain on the ohmic contact layer, wherein at least a portion of the ohmic contact layer located between the source and the drain is removed.
7. The manufacturing process of the thin film transistor of claim 6, wherein forming the ohmic contact layer comprises:
utilizing a deposition process, wherein a deposition power is changed during the deposition process so as to form the N-doped amorphous silicon layers to constitute the ohmic contact layer having the N-doped amorphous silicon layers.
8. The manufacturing process of the thin film transistor of claim 7, wherein a way to change the deposition power during the deposition process comprises turning off the power at a predetermined time interval during the deposition process.
9. The manufacturing process of the thin film transistor of claim 6, wherein forming the ohmic contact layer comprises:
utilizing a deposition process, wherein a deposition pressure condition is changed during the deposition process so as to form the N-doped amorphous silicon layers to constitute the ohmic contact layer having the N-doped amorphous silicon layers.
10. The manufacturing process of the thin film transistor of claim 9, wherein a way to change the deposition pressure condition during the deposition process comprises changing the pressure at a predetermined time interval during the deposition process, so as to lower the deposition rate.