Scan-based MCM interconnecting testing
A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.
1. A multi-die chip module (MCM), comprising:
a first die containing a first test controller; and
a second die containing a second test controller and coupled to the first die via an interconnect, said interconnect comprising multiple signal lines;
wherein the first test controller is configured to place the first die to be in one of a shift mode and a capture mode while the second controller is configured to place the second die in the other of the shift mode and capture mode; and
wherein after a scan shift operation, scan cells are initialized to predetermined values and during the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.
2. The MCM of claim 1 wherein the second die comprises scan clock logic to generate a variable frequency MCM scan clock used during the capture mode, said MCM scan clock also provided to the first die, and wherein shifting of data into the registers occurs by way of a first frequency of the MCM scan clock, and capture occurs by way of a second frequency of the MCM scan clock.
3. The MCM of claim 2 wherein the second frequency is greater than the first frequency.
4. The MCM of claim 2 wherein, when the second die is in the shift mode and the first die is in the capture mode, a rising edge of the MCM scan clock on the second die is used to launch a bit to output pads of the second die, and a falling edge of the MCM scan clock on the first die is used to capture bits on input pads of the first die.
5. The MCM of claim 4 wherein, when the first die in the launch mode and the second die is in the capture mode, a rising edge of the MCM scan clock on the first die is used to launch a bit to output pads of the first die, and a rising edge of the MCM scan clock on the second die is used to capture bits on input pads of the second die.
6. The MCM of claim 1 wherein each test controller receives a separate scan enable signal, each such scan enable signal causes the respective test controller to be in the shift mode or the capture mode.
7. A multi-die chip module (MCM), comprising:
a first die containing a first test controller and a plurality of input/output (I/O) pads; and
a second die containing a second test controller and a plurality of I/O pads, the I/O pads of the second die electrically connected via an electrical interconnect to the I/O pads of the first die;
a plurality of scan cells, a scan cell corresponding to each I/O pad of the first die and the second die, and the scan cells connected in a scan chain;
wherein the first test controller is configured to place the first die to be in one of a shift mode and a capture mode while the second controller is configured to place the second die in the other of the shift mode and capture mode, so that as test bits are shifted into scan cells associated with output pads on the die in the shift mode, the other die is in the capture mode and its scan cells captures signal received across the electrical interconnect, without the die in the shift mode performing an update operation to latch in the test bits before their capture by the second die.
8. The MCM of claim 7 wherein each scan cell includes an update register that is implemented as a transparent latch to permit a test bit shifted into a serial register to be provided straight through to the I/O pad corresponding to that scan cell.
9. The MCM of claim 7 wherein the second die comprises scan clock logic to generate a variable frequency MCM scan clock used during the capture mode, said MCM scan clock also provided to the first die, and wherein shifting of data into the registers occurs by way of a first frequency of the MCM scan clock, and capture occurs by way of a second frequency of the MCM scan clock.
10. The MCM of claim 9 wherein the second frequency is greater than the first frequency.
11. The MCM of claim 9 wherein, when the second die is in the shift mode and the first die is in the capture mode, a rising edge of the MCM scan clock on the second die is used to launch a bit to output pads of the second die, and a falling edge of the MCM scan clock on the first die is used to capture bits on input pads of the first die.
12. The MCM of claim 11 wherein, when the first die in the launch mode and the second die is in the capture mode, a rising edge of the MCM scan clock on the first die is used to launch a bit to output pads of the first die, and a rising edge of the MCM scan clock on the second die is used to capture bits on input pads of the second die.
13. The MCM of claim 7 wherein each test controller receives a separate scan enable signal, each such scan enable signal causes the respective test controller to be in the shift mode or the capture mode.