Transistor with minimized resistance

1. A power transistor array, the power transistor array comprising:

a bottom metal layer including a plurality of strips, each corresponding to either drain or source strips, the drain and source strips being placed in parallel and alternating with each other;

a top metal layer, above the bottom metal layer, including a plurality of strips, each strip corresponding to either drain or source strips, the drain and source strips being placed in parallel and alternating with each other, wherein the strips of the top metal layer are oriented at angle with respect to the strips of the bottom metal layer;

a plurality of bond pads placed on the strips of the top metal layer, wherein each of the plurality of bond pads is arranged at a center of a respective strip such that a uniform current distribution through said metal layers is achieved; and

a plurality of bond wires, each bond wire having one end attached to the corresponding bond pad.

2. The power transistor array of claim 1 further comprising one or more of the following metal layers, wherein each metal layer includes a plurality of strips, each corresponding to either drain or source strips, the drain and source strips being placed in parallel and alternating with each other:

a first metal layer formed over the bottom metal layer, the strips of the first metal layer running in parallel to one another above the strips of the bottom metal layer;

a second metal layer formed over the first metal layer, wherein the strips of the second metal layer are oriented perpendicular to the strips of the first metal layer below it;

a third metal layer formed over the second metal layer, wherein the strips of the third metal layer are oriented diagonally with respect to the strips of the second metal layer below it;

a fourth metal layer formed over the third metal layer and below the top metal layer, wherein the strips of the fourth metal layer are oriented perpendicular to the strips of the third metal layer below it; and

the top metal layer formed over the fourth metal layer, wherein the strips of the top metal layer are oriented perpendicular to the strips of the fourth metal layer below it.

3. The power transistor array of claim 2 , wherein the strips of the first metal layer are oriented perpendicular to the strips of the bottom metal layer.

4. The power transistor array of claim 2 , wherein all metal layers below the top metal layer run in parallel to each other.

5. The power transistor array of claim 2 , wherein the strips of the first metal layer are wider than the strips of the bottom metal layer.

6. The power transistor array of claim 1 , wherein the strips of the top metal layer having a low resistance relative to the strips of the bottom metal layer.

7. The power transistor array of claim 1 , wherein the metal layers are interconnected by means of vias, wherein a plurality of vias connect a strip of the bottom layer with a strip of the top layer.

8. The power transistor array of claim 7 , wherein the number of vias and location of the vias is chosen to minimize the resistance path through the transistors of the array.

9. A power transistor array, comprising:

a plurality of metal layers, each layer including a plurality of strips, each strip corresponding to either a drain strip or a source strip, wherein the metal layers include at least two of:

a bottom metal layer, the strips of the bottom metal layer being arranged in parallel and alternating as drain strips and source strips, a first metal layer formed over the bottom metal layer, the strips of the first metal layer running in parallel to one another above the strips of the bottom metal layer;

a second metal layer formed over the first metal layer, wherein the strips of the second metal layer are oriented perpendicular to the strips of the first metal layer;

a third metal layer formed over the second metal layer, wherein the strips of the third metal layer are oriented diagonally with respect to the strips of the second metal layer;

a fourth metal layer formed over the third metal layer, wherein the strips of the fourth metal layer are oriented perpendicular to the strips of the third metal layer; and

a top metal layer formed over the fourth metal layer, the strips of the top metal layer being oriented perpendicular with respect to the strips of the fourth metal layer, and

a plurality of drain and source bond pads each arranged near a center region of a respective strip, respectively such that a uniform current distribution through said metal layers is achieved, the bond pads connecting to the drain and source strips of the top metal layer, respectively.

10. The power transistor array of claim 9 further comprising at least one bond wire corresponding to each bond pad.

11. The power transistor array of claim 9 , wherein each of the bond pads is formed in the middle of the strips of the top metal layer.

12. The power transistor array of claim 9 further comprising a plurality of vias formed between the strips of the metal layers.

13. A semiconductor integrated circuit comprising:

a transistor array having a bottom metal layer and a top metal layer formed over the transistor, the bottom metal layer including a plurality of strips, each corresponding to either a drain or a source of a transistor of the transistor array, the drain and source strips being placed in parallel and alternating with each other, and

the top metal layer being formed over the bottom metal layer, and including a plurality of strips, each strip corresponding to either a drain or a source of the transistor, the drain and source strips being placed in parallel and alternating with each other, wherein the strips of the top metal layer are oriented diagonally with respect to the strips of the bottom metal layer;

a plurality of bond pads, each being placed in a center of a respective strips of the top metal layer such that a uniform current distribution through said metal layers is achieved; and

a plurality of bond wires, each bond wire having one end attached to the corresponding bond pad.

14. The power transistor array of claim 1 , wherein the strips of the top metal layer are oriented diagonally with respect to the strips of the bottom metal layer.