Audio processing devices with port output circuits controlled by PC beep signal activity
View Patent ↗An audio processing integrated circuit chip, such as codec chip, includes at least one port output circuit configured to generate an audio signal to drive an external audio device and a PC beep circuit configured to receive a PC beep signal and to apply the received PC beep signal to an input of the at least one port output circuit. The chip further includes a control circuit configured to detect activity of the PC beep signal and to enable and/or disable the at least one port output circuit responsive to the detected activity.
1. An audio processing integrated circuit chip comprising:
at least one port output circuit configured to drive an external audio device;
a PC beep circuit configured to receive a PC beep signal and to drive the at least one port output circuit responsive to the PC beep signal; and
a control circuit configured to detect activity of the PC beep signal and to enable and/or disable the at least one port output circuit responsive to the detected activity, the control circuit comprising:
a beep signal sensor circuit configured to compare the PC beep signal to a reference signal to thereby generate a beep sense signal;
an activity detector circuit configured to monitor the beep sense signal and to responsively generate a beep activity detection signal; and
a port output control circuit configured to control the at least one port output circuit responsive to the beep activity detection signal.
2. The audio processing integrated circuit chip of claim 1 , wherein the control circuit is configured to enable and/or disable the at least one port output circuit responsive to the detected activity meeting a criterion.
3. The audio processing integrated circuit chip of claim 1 , wherein the activity detector circuit is configured to determine a duration for which the beep sense signal remains in a given state and to responsively generate the beep activity detection signal.
4. The audio processing integrated circuit chip of claim 1 , further comprising a link reset input configured to receive a link reset signal, and wherein the control circuit is configured to operate responsive to the link reset signal.
5. The audio processing integrated circuit chip of claim 1 , wherein the control circuit is configured to disable the at least one port output circuit for a time interval responsive to power up of the audio processing integrated circuit chip.
6. An audio codec integrated circuit chip comprising:
a digital bus interface circuit configured to receive digital audio signals over a digital communications bus;
a plurality of audio ports configured to be coupled to external audio devices;
audio processing circuitry configured to process the digital audio signals received by the digital bus interface circuit to produce processed audio signals;
a plurality of port output circuits configured to generate audio signals at the audio ports responsive to the processed audio signals;
a PC beep circuit configured to receive a PC beep signal from the host and to drive at least one of the port output circuits responsive to the PC beep signal; and
a control circuit configured to detect activity of the PC beep signal and to enable and/or disable the at least one of the port output circuits responsive to the detected activity, the control circuit comprising:
a beep signal sensor circuit configured to compare the PC beep signal to a reference signal to thereby generate a beep sense signal;
an activity detector circuit configured to monitor the beep sense signal and to responsively generate a beep activity detection signal; and
a port output control circuit configured to control the at least one port output circuit responsive to the beep activity detection signal.
7. The audio codec integrated circuit chip of claim 6 , wherein the control circuit is configured to enable and/or disable the at least one of the port output circuits responsive to the detected activity meeting a criterion.
8. The audio codec integrated circuit chip of claim 6 , further comprising a link reset input configured to receive a link reset signal and wherein the control circuit is configured to operate responsive to the link reset signal.
9. The audio codec integrated circuit chip of claim 6 , wherein the control circuit is configured to disable the at least one of the port output circuits for a time interval responsive to power up of the audio processing integrated circuit chip.
10. An audio processing integrated circuit chip comprising:
at least one port output circuit configured to drive an external audio device;
a PC beep circuit configured to receive a PC beep signal and drive the at least one port output circuit responsive to the PC beep signal; and
a control circuit configured to determine whether activity at an input of the PC beep circuit meets a criterion and to responsively control power consumption by the audio processing integrated circuit chip, the control circuit comprising:
a beep signal sensor circuit configured to compare the PC beep signal to a reference signal to thereby generate a beep sense signal;
an activity detector circuit configured to monitor the beep sense signal and to responsively generate a beep activity detection signal; and
a port output control circuit configured to control the at least one port output circuit responsive to the beep activity detection signal.
11. The audio processing integrated circuit chip of claim 10 , further comprising a link reset input configured to receive a link reset signal and wherein the control circuit is configured to operate responsive to the link reset signal.
12. The audio processing integrated circuit chip of claim 10 , wherein the control circuit is configured to disable the at least one port output circuit for a time interval responsive to power up of the audio processing integrated circuit chip.